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Brigham Young University - Provo

Low-Voltage Analog CMOS Architectures and Design Methods

Abstract

dc:description.abstract

This dissertation develops design methods and architectures which allow analog circuits to operate at VT + 2Vds,sat, the minimum supply for CMOS circuits with all transistors in the active region where Vds,sat is the drain to source saturation voltage of a MOS transistor. Techniques which meet this criteria for rail-to-rail input stages, gain enhancement stages, and output stages are discussed and developed. These techniques are used to design four fully-differential rail-to-rail amplifiers. The highest gain is shown to be attained using a drain voltage equalization (DVE) or active-bootstrapping technique which produces more than 100dB of gain in a two stage amplifier with a bulk-driven input pair while showing no bandwidth degradation when compared to amplifier architectures with similar biasing. The low voltage design techniques are extended to switching and sampling circuits. A 10-bit digital to analog converter (DAC) and a 10-bit analog to digital converter (ADC) are designed and fabricated in a 0.35um dual-well CMOS process to prove the developed design methods, architectures, and techniques. The 10-bit DAC operates at 1MSPS with near rail-to-rail differential output operation with a 700mV supply voltage. This supply voltage, which is 150mV lower than the VT+2Vds,sat limit, is attained by using a bulk driven threshold voltage lowering technique. The ADC design is a fully-differential pipelined 10-bit converter that operates at 500kSPS with a full scale input range equal to the supply voltage and can operate at supply voltages as low as 650mV, 200mV below the VT + 2Vds,sat limit. The design methods and architectures can be used in advanced processes to maintain gain and minimize supply voltage. These designs show a minimum supply improvement over previously published designs and prove the efficacy of the design architectures and techniques presented in this dissertation.

Degree

thesis:*
Name thesis:degree_name
PhD
Grantor dc:publisher
Brigham Young University - Provo

Author and committee

dc:creator, dc:contributor.*
Author dc:creator
  • Layton, Kent Downing

Subjects

dc:subject × 10

Rights

Language dc:language
English

Identifiers

dc:identifier.*
Repository record dc:identifier
https://scholarsarchive.byu.edu/etd/1218
OAI identifier oai:identifier
oai:scholarsarchive.byu.edu:etd-2217

Chain of custody

source
Harvested from
Brigham Young University
Base URL
scholarsarchive.byu.edu/do/oai/
Last updated
2026-07-24
Source record
OAI-PMH GetRecord
citation

Layton, Kent Downing. Low-Voltage Analog CMOS Architectures and Design Methods. Brigham Young University - Provo, https://scholarsarchive.byu.edu/etd/1218