Using Duplication with Compare for On-line Error Detection in FPGA-based Designs

<p>Space destined FPGA-based systems must employ redundancy techniques to account for the effects of upsets caused by radiated environments. Error detection techniques can be used to alert external systems to the presence of these upsets. Readback with compare is an error detection technique commonly employed in FPGA-based designs. This work introduces duplication with compare (DWC) as an automated on-line error detection technique that can be used as an alternative to readback with compare. This work also introduces a set of metrics that is used to quantify the effectiveness and coverage of this error detection technique. A tool is presented that automatically inserts duplication with compare into a user's design. Duplication with compare is shown to correctly detect over 99.9% of errors caused by configuration upsets at a hardware cost of approximately 2X. System designers can apply duplication with compare to designs using this tool to increase the reliability and availability of their systems while minimizing resource usage and power.</p>

Name thesis:degree_name

MS

Grantor dc:publisher

Brigham Young University - Provo

Author dc:creator

• McMurtrey, Daniel L.

• error detection
• FPGA
• SEU
• reliability
• FPGA reliability
• soft errors
• fault tolerance
• Electrical and Computer Engineering

Language dc:language

English

Repository record dc:identifier

https://scholarsarchive.byu.edu/etd/1094

OAI identifier oai:identifier

oai:scholarsarchive.byu.edu:etd-2093