Hardware Support for a Configurable Architecture for Real-Time Embedded Systems on a Programmable Chip

Current FPGA technology has advanced to the point that useful embedded SoPCs can now be designed. The Real Time Processor (RTP) project at Brigham Young University leverages the advances in FPGA technology with a system architecture that is customizable to specific applications. A simple real-time processor has been designed to provide support for a hardware-assisted real-time operating system providing fast context switches. As part of the hardware RTOS, the following have been implemented in hardware: scheduler, register banks, mutex, semaphore, queue, interrupts, event, and others. A novel circuit called the Task-Resource Matrix has been created to allow fast inter/intra processor communication and synchronization.

Name thesis:degree_name

MS

Grantor dc:publisher

Brigham Young University - Provo

Author dc:creator

• Isaacson, Spencer W.

• FPGA
• hardware RTOS
• real-time
• fast context switch
• register bank
• task
• task-resource matrix
• embedded
• computer architecture
• hardware scheduler
• task switch
• hardware assisted RTOS
• Electrical and Computer Engineering

Language dc:language

English

Repository record dc:identifier

https://scholarsarchive.byu.edu/etd/971

OAI identifier oai:identifier

oai:scholarsarchive.byu.edu:etd-1970