Accelerating path planning algorithms with high level synthesis tools and FPGAs.

Accelerating path planning algorithms with field programmable gate arrays (FPGA) allows the designer to achieve significant performance increases over using a traditional central processing unit (CPU). Converting an algorithm to run on an FPGA is a complicated and time consuming process. This thesis develops and verifies a design framework that demonstrates how to design a path planning algorithm in a high level language, then convert the algorithm into hardware description languages using high level synthesis tools. This design framework will be used to demonstrate the acceleration of a genetic algorithm.

Name thesis:degree_name

M.S.E.C.E.

Level thesis:degree_level

Masters

Grantor

Baylor University.

Year dc:date.issued

2012

Author dc:creator

• Trower, John W.

Advisor dc:contributor.advisor

• Duren, Russell Walker.

• Path planning algorithms.
• Field programmable gate array (FPGA)
• High level synthesis tools.
• Converting algorithms.

Statement dc:rights

• Baylor University works are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. Contact libraryquestions@baylor.edu for inquiries about permission.

Language dc:language.iso

en

Handle dc:identifier.uri

https://hdl.handle.net/2104/8600

OAI identifier oai:identifier

oai:baylor-ir.tdl.org:2104/8600