{"id":{"repo_id":"baylor","oai_identifier":"oai:baylor-ir.tdl.org:2104/8600"},"canonical_url":"https://search.dev.ndltd.org/etd/baylor/oai:baylor-ir.tdl.org:2104/8600","repository":{"repo_id":"baylor","name":"Baylor University","base_url":"https://baylor-ir.tdl.org/server/oai/request"},"display":{"title":"Accelerating path planning algorithms with high level synthesis tools and FPGAs.","abstract":"Accelerating path planning algorithms with field programmable gate arrays (FPGA) allows the designer to achieve significant performance increases over using a traditional central processing unit (CPU). Converting an algorithm to run on an FPGA is a complicated and time consuming process. This thesis develops and verifies a design framework that demonstrates how to design a path planning algorithm in a high level language, then convert the algorithm into hardware description languages using high level synthesis tools. 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