Design and automated testing of PCI express interface of proton computed tomography detectors.

Throughout this thesis, I will propose a transmit-received-engine based logic design proposed by this thesis works at the PCI Express Transaction Layer in collaboration with Xilinx 7 Series FPGAs Integrated Block for PCI Express. By automated testing and results evaluation, the new design can speed up the original Ethernet link speed by a factor of 30, At the same time, supports the needs of the new signal peaks in 50 ns. Therefore, two key concerns of the existing Phase-II pCT scanner hardware upgrade can be satisfied.

Name thesis:degree_name

M.S.E.C.E.

Level thesis:degree_level

Masters

Grantor

Baylor University.

Year dc:date.issued

2019

Author dc:creator

• Yang, Yu, 1989-

Advisor dc:contributor.advisor

• Schubert, Keith Evan.

• Computer engineering.
• Tomography detectors.
• PCI Express Transaction Layer.

Statement dc:rights

• Baylor University works are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. Contact libraryquestions@baylor.edu for inquiries about permission.

Language dc:language.iso

en

Handle dc:identifier.uri

https://hdl.handle.net/2104/10686

OAI identifier oai:identifier

oai:baylor-ir.tdl.org:2104/10686