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University of Arkansas

Non-Volatile Memory Adaptation in Asynchronous Microcontroller for Low Leakage Power and Fast Turn-on Time

Abstract

dc:description.abstract

<p>This dissertation presents an MSP430 microcontroller implementation using Multi-Threshold NULL Convention Logic (MTNCL) methodology combined with an asynchronous non-volatile magnetic random-access-memory (RAM) to achieve low leakage power and fast turn-on. This asynchronous non-volatile RAM is designed with a Spin-Transfer Torque (STT) memory device model and CMOS transistors in a 65 nm technology. A self-timed Quasi-Delay-Insensitive 1 KB STT RAM is designed with an MTNCL interface and handshaking protocol. A replica methodology is implemented to handle write operation completion detection for long state-switching delays of the STT memory device. The MTNCL MSP430 core is integrated with the STT RAM to create a fully asynchronous non-volatile microcontroller. </p> <p>The MSP430 architecture, the MTNCL design methodology, and the STT RAM’s low power property, along with STT RAM’s non-volatility yield multiple advantages in the MTNCL-STT RAM system for a variety of applications. For comparison, a baseline system with the same MTNCL core combined with an asynchronous CMOS RAM is designed and tested. Schematic simulation results demonstrate that the MTNCL-CMOS RAM system presents advantages in execution time and active energy over the MTNCL-STT RAM system; however, the MTNCL-STT RAM system presents unmatched advantages such as negligible leakage power, zero overhead memory power failure handling, and fast system turn-on. </p>

Degree

thesis:*
Name thesis:degree_name
Doctor of Philosophy in Engineering (PhD)
Level thesis:degree_level
Dissertation
Year dc:date.available
2021

Author and committee

dc:creator, dc:contributor.*
Author dc:creator
  • Habimana, Jean Pierre Thierry
Advisor dc:contributor.advisor
  • Di, Jia
Contributors dc:contributor
  • Parkerson, James P.
  • Wu, Jingxian

Subjects

dc:subject × 8

Identifiers

dc:identifier.*
Repository record dc:identifier
https://scholarworks.uark.edu/etd/3998
OAI identifier oai:identifier
oai:scholarworks.uark.edu:etd-5548

Chain of custody

source
Harvested from
University of Arkansas
Base URL
scholarworks.uark.edu/do/oai/
Last updated
2026-07-24
Source record
OAI-PMH GetRecord
citation

Habimana, Jean Pierre Thierry. Non-Volatile Memory Adaptation in Asynchronous Microcontroller for Low Leakage Power and Fast Turn-on Time. Dissertation thesis, 2021. https://scholarworks.uark.edu/etd/3998