Asynchronous Circuit Stacking for Simplified Power Management

<p>As digital integrated circuits (ICs) continue to increase in complexity, new challenges arise for designers. Complex ICs are often designed by incorporating multiple power domains therefore requiring multiple voltage converters to produce the corresponding supply voltages. These converters not only take substantial on-chip layout area and/or off-chip space, but also aggregate the power loss during the voltage conversions that must occur fast enough to maintain the necessary power supplies. This dissertation work presents an asynchronous Multi-Threshold NULL Convention Logic (MTNCL) “stacked” circuit architecture that alleviates this problem by reducing the number of voltage converters needed to supply the voltage the ICs operate at. By stacking multiple MTNCL circuits between power and ground, supplying a multiple of VDD to the entire stack and incorporating simple control mechanisms, the dynamic range fluctuation problem can be mitigated. A 130nm Bulk CMOS process and a 32nm Silicon-on-Insulator (SOI) CMOS process are used to evaluate the theoretical effect of stacking different circuitry while running different workloads. Post parasitic physical implementations are then carried out in the 32nm SOI process for demonstrating the feasibility and analyzing the advantages of the proposed MTNCL stacking architecture. </p>

Name thesis:degree_name

Doctor of Philosophy in Engineering (PhD)

Level thesis:degree_level

Dissertation

Year dc:date.available

2018

Author dc:creator

• Suchanek, Andrew Lloyd

Advisor dc:contributor.advisor

• Di, Jia

Contributors dc:contributor

• Parkerson, James P.
• Thompson, Dale R.

• Asynchronous
• Low-power
• MTNCL
• Voltage Stacking
• Digital Circuits

Repository record dc:identifier

https://scholarworks.uark.edu/etd/2805

OAI identifier oai:identifier

oai:scholarworks.uark.edu:etd-4354