Radiation-Hardened Delay-Insensitive Asynchronous Circuits for Multi-Bit SEU Mitigation and Data-Retaining SEL Protection

<p>Radiation can have highly damaging effects on circuitry, especially for space applications, if designed without radiation-hardening mechanisms. Delay-insensitive asynchronous circuits inherently have promising potentials in mitigating the effects of radiation due to their delay insensitivity. This thesis proposes the use of two delay-insensitive asynchronous logic architectures to mitigate the effects of up to two single-event upsets (SEU) and a single-event latch-up (SEL). The multi-bit SEU mitigation with SEL protection architecture improves the original design by providing more integrity against data corruption and lock-ups caused by multi-bit SEUs, and it is expanded to simultaneously provide protection against SEL. The multi-bit SEU mitigation with data-retaining SEL protection architecture extends the original architecture by guaranteeing no data loss during the power cycling for mitigating SEL. The results show that the proposed architectures function correctly, at the transistor level, in mitigating up to two SEUs and an SEL without data loss. </p>

Name thesis:degree_name

Master of Science in Computer Engineering (MSCmpE)

Level thesis:degree_level

Thesis

Year dc:date.available

2014

Author dc:creator

• Brady, John Davis

Advisor dc:contributor.advisor

• Di, Jia

Contributors dc:contributor

• Parkerson, James P.
• Thompson, Dale R.

• Asynchronous
• Radiation Hardening
• SEL Protection
• SEU Mitigation
• Digital Circuits

Repository record dc:identifier

https://scholarworks.uark.edu/etd/2299

OAI identifier oai:identifier

oai:scholarworks.uark.edu:etd-3838