Radiation can have highly damaging effects on circuitry, especially for space applications, if designed without radiation-hardening mechanisms. Delay-insensitive asynchronous circuits inherently have promising potentials in mitigating the effects of radiation due to their delay insensitivity. This thesis proposes the use of two delay-insensitive asynchronous logic architectures to mitigate the effects of up to two single-event upsets (SEU) and a single-event latch-up (SEL). The multi-bit SEU mitigation with SEL protection architecture improves the original design by providing more integrity against data corruption and lock-ups caused by multi-bit SEUs, and it is expanded to simultaneously provide protection against SEL. The multi-bit SEU mitigation with data-retaining SEL protection architecture extends the original architecture by guaranteeing no data loss during the power cycling for mitigating SEL. The results show that the proposed architectures function correctly, at the transistor level, in mitigating up to two SEUs and an SEL without data loss.
","abstract_html":"<p>Radiation can have highly damaging effects on circuitry, especially for space applications, if designed without radiation-hardening mechanisms. Delay-insensitive asynchronous circuits inherently have promising potentials in mitigating the effects of radiation due to their delay insensitivity. This thesis proposes the use of two delay-insensitive asynchronous logic architectures to mitigate the effects of up to two single-event upsets (SEU) and a single-event latch-up (SEL). The multi-bit SEU mitigation with SEL protection architecture improves the original design by providing more integrity against data corruption and lock-ups caused by multi-bit SEUs, and it is expanded to simultaneously provide protection against SEL. The multi-bit SEU mitigation with data-retaining SEL protection architecture extends the original architecture by guaranteeing no data loss during the power cycling for mitigating SEL. The results show that the proposed architectures function correctly, at the transistor level, in mitigating up to two SEUs and an SEL without data loss. </p>","abstract_has_math":false,"creators":["Brady, John Davis"],"institution":null,"degree_name":"Master of Science in Computer Engineering (MSCmpE)","degree_level":"Thesis","degree_discipline":null,"degree_department":null,"school":null,"contributors":["Parkerson, James P.","Thompson, Dale R."],"advisors":["Di, Jia"],"committee_chairs":[],"committee_members":[],"year":2014,"date_issued":"2014-05-01T07:00:00Z","date_published":"2014-05-01T07:00:00Z","updated_at":"2026-07-24T00:59:24Z","subjects":["Asynchronous","Radiation Hardening","SEL Protection","SEU Mitigation","Digital Circuits"],"languages":[],"rights":[],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://scholarworks.uark.edu/etd/2299","outbound_label":"Repository record","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Parkerson, James P.","Thompson, Dale R."]},{"key":"dc:contributor.advisor","label":"Advisor","values":["Di, Jia"]},{"key":"dc:creator","label":"Author","values":["Brady, John Davis"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2014"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2024-02-06T08:00:00Z"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Master of Science in Computer Engineering (MSCmpE)"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Asynchronous","Radiation Hardening","SEL Protection","SEU Mitigation","Digital Circuits"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://scholarworks.uark.edu/etd/2299"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["Radiation can have highly damaging effects on circuitry, especially for space applications, if designed without radiation-hardening mechanisms. Delay-insensitive asynchronous circuits inherently have promising potentials in mitigating the effects of radiation due to their delay insensitivity. This thesis proposes the use of two delay-insensitive asynchronous logic architectures to mitigate the effects of up to two single-event upsets (SEU) and a single-event latch-up (SEL). The multi-bit SEU mitigation with SEL protection architecture improves the original design by providing more integrity against data corruption and lock-ups caused by multi-bit SEUs, and it is expanded to simultaneously provide protection against SEL. The multi-bit SEU mitigation with data-retaining SEL protection architecture extends the original architecture by guaranteeing no data loss during the power cycling for mitigating SEL. The results show that the proposed architectures function correctly, at the transistor level, in mitigating up to two SEUs and an SEL without data loss.
"]},{"key":"dc:title","label":"Title","values":["Radiation-Hardened Delay-Insensitive Asynchronous Circuits for Multi-Bit SEU Mitigation and Data-Retaining SEL Protection"]}]}],"canonical_facts":{"dc:contributor":["Parkerson, James P.","Thompson, Dale R."],"dc:contributor.advisor":["Di, Jia"],"dc:creator":["Brady, John Davis"],"dc:date":["2014"],"dc:date.available":["2024-02-06T08:00:00Z"],"dc:description.abstract":["Radiation can have highly damaging effects on circuitry, especially for space applications, if designed without radiation-hardening mechanisms. Delay-insensitive asynchronous circuits inherently have promising potentials in mitigating the effects of radiation due to their delay insensitivity. This thesis proposes the use of two delay-insensitive asynchronous logic architectures to mitigate the effects of up to two single-event upsets (SEU) and a single-event latch-up (SEL). The multi-bit SEU mitigation with SEL protection architecture improves the original design by providing more integrity against data corruption and lock-ups caused by multi-bit SEUs, and it is expanded to simultaneously provide protection against SEL. The multi-bit SEU mitigation with data-retaining SEL protection architecture extends the original architecture by guaranteeing no data loss during the power cycling for mitigating SEL. The results show that the proposed architectures function correctly, at the transistor level, in mitigating up to two SEUs and an SEL without data loss.
"],"dc:identifier":["https://scholarworks.uark.edu/etd/2299"],"dc:subject":["Asynchronous","Radiation Hardening","SEL Protection","SEU Mitigation","Digital Circuits"],"dc:title":["Radiation-Hardened Delay-Insensitive Asynchronous Circuits for Multi-Bit SEU Mitigation and Data-Retaining SEL Protection"],"thesis:degree_level":["Thesis"],"thesis:degree_name":["Master of Science in Computer Engineering (MSCmpE)"]},"updated_at":"2026-07-24T00:59:24Z"}