Electrical Design Considerations and Packaging of Power Electronic Modules

<p>A modern power electronic module can save significant energy usage in the power electronic systems by improving their switching efficiencies. One way to improve the efficiency of the power electronic module is to reduce its parasitic circuit elements. The purpose of this thesis is to investigate the mitigation of parasitic circuit elements in power electronic modules. General methods of mitigating parasitic inductances were analyzed by the Q3D Extractor and verified by the time-domain reflectometry (TDR) measurements. In most cases, the TDR measurement results closely matched those predicted by the Q3D Extractor. These methods were applied to design and analyze a 50KVA 650V silicon carbide (SiC) half-bridge power electronic power module consisting of three separate power substrates interconnected in parallel. The layout of this power module was constrained by the existing module housing. The parasitic inductances of the power module substrates were measured by TDR, and compared to those simulated values by the Q3D Extractor. Due to the differences in the lengths of current paths, the parasitic circuit elements for the three paralleled SiC power substrates, each consisting of 10 SiC power MOSFETs and 9 SiC diodes, were different.</p>

Name thesis:degree_name

Master of Science in Electrical Engineering (MSEE)

Level thesis:degree_level

Thesis

Year dc:date.available

2013

Author dc:creator

• Wang, Shijie

Advisor dc:contributor.advisor

• Ang, Simon S.

Contributors dc:contributor

• Balda, Juan C.
• Brown, Randy L.

• Applied sciences
• Parasitic inductance
• Power electronics
• Power module
• Semiconductor devices
• Electrical and Electronics
• Electronic Devices and Semiconductor Manufacturing
• Power and Energy

Repository record dc:identifier

https://scholarworks.uark.edu/etd/858

OAI identifier oai:identifier

oai:scholarworks.uark.edu:etd-1857