A modern power electronic module can save significant energy usage in the power electronic systems by improving their switching efficiencies. One way to improve the efficiency of the power electronic module is to reduce its parasitic circuit elements. The purpose of this thesis is to investigate the mitigation of parasitic circuit elements in power electronic modules. General methods of mitigating parasitic inductances were analyzed by the Q3D Extractor and verified by the time-domain reflectometry (TDR) measurements. In most cases, the TDR measurement results closely matched those predicted by the Q3D Extractor. These methods were applied to design and analyze a 50KVA 650V silicon carbide (SiC) half-bridge power electronic power module consisting of three separate power substrates interconnected in parallel. The layout of this power module was constrained by the existing module housing. The parasitic inductances of the power module substrates were measured by TDR, and compared to those simulated values by the Q3D Extractor. Due to the differences in the lengths of current paths, the parasitic circuit elements for the three paralleled SiC power substrates, each consisting of 10 SiC power MOSFETs and 9 SiC diodes, were different.
","abstract_html":"<p>A modern power electronic module can save significant energy usage in the power electronic systems by improving their switching efficiencies. One way to improve the efficiency of the power electronic module is to reduce its parasitic circuit elements. The purpose of this thesis is to investigate the mitigation of parasitic circuit elements in power electronic modules. General methods of mitigating parasitic inductances were analyzed by the Q3D Extractor and verified by the time-domain reflectometry (TDR) measurements. In most cases, the TDR measurement results closely matched those predicted by the Q3D Extractor. These methods were applied to design and analyze a 50KVA 650V silicon carbide (SiC) half-bridge power electronic power module consisting of three separate power substrates interconnected in parallel. The layout of this power module was constrained by the existing module housing. The parasitic inductances of the power module substrates were measured by TDR, and compared to those simulated values by the Q3D Extractor. Due to the differences in the lengths of current paths, the parasitic circuit elements for the three paralleled SiC power substrates, each consisting of 10 SiC power MOSFETs and 9 SiC diodes, were different.</p>","abstract_has_math":false,"creators":["Wang, Shijie"],"institution":null,"degree_name":"Master of Science in Electrical Engineering (MSEE)","degree_level":"Thesis","degree_discipline":null,"degree_department":null,"school":null,"contributors":["Balda, Juan C.","Brown, Randy L."],"advisors":["Ang, Simon S."],"committee_chairs":[],"committee_members":[],"year":2013,"date_issued":"2013-08-01T07:00:00Z","date_published":"2013-08-01T07:00:00Z","updated_at":"2026-07-24T01:00:19Z","subjects":["Applied sciences","Parasitic inductance","Power electronics","Power module","Semiconductor devices","Electrical and Electronics","Electronic Devices and Semiconductor Manufacturing","Power and Energy"],"languages":[],"rights":[],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://scholarworks.uark.edu/etd/858","outbound_label":"Repository record","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Balda, Juan C.","Brown, Randy L."]},{"key":"dc:contributor.advisor","label":"Advisor","values":["Ang, Simon S."]},{"key":"dc:creator","label":"Author","values":["Wang, Shijie"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2013"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2017-09-29T07:00:00Z"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Master of Science in Electrical Engineering (MSEE)"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Applied sciences","Parasitic inductance","Power electronics","Power module","Semiconductor devices","Electrical and Electronics","Electronic Devices and Semiconductor Manufacturing","Power and Energy"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://scholarworks.uark.edu/etd/858"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["A modern power electronic module can save significant energy usage in the power electronic systems by improving their switching efficiencies. One way to improve the efficiency of the power electronic module is to reduce its parasitic circuit elements. The purpose of this thesis is to investigate the mitigation of parasitic circuit elements in power electronic modules. General methods of mitigating parasitic inductances were analyzed by the Q3D Extractor and verified by the time-domain reflectometry (TDR) measurements. In most cases, the TDR measurement results closely matched those predicted by the Q3D Extractor. These methods were applied to design and analyze a 50KVA 650V silicon carbide (SiC) half-bridge power electronic power module consisting of three separate power substrates interconnected in parallel. The layout of this power module was constrained by the existing module housing. The parasitic inductances of the power module substrates were measured by TDR, and compared to those simulated values by the Q3D Extractor. Due to the differences in the lengths of current paths, the parasitic circuit elements for the three paralleled SiC power substrates, each consisting of 10 SiC power MOSFETs and 9 SiC diodes, were different.
"]},{"key":"dc:title","label":"Title","values":["Electrical Design Considerations and Packaging of Power Electronic Modules"]}]}],"canonical_facts":{"dc:contributor":["Balda, Juan C.","Brown, Randy L."],"dc:contributor.advisor":["Ang, Simon S."],"dc:creator":["Wang, Shijie"],"dc:date":["2013"],"dc:date.available":["2017-09-29T07:00:00Z"],"dc:description.abstract":["A modern power electronic module can save significant energy usage in the power electronic systems by improving their switching efficiencies. One way to improve the efficiency of the power electronic module is to reduce its parasitic circuit elements. The purpose of this thesis is to investigate the mitigation of parasitic circuit elements in power electronic modules. General methods of mitigating parasitic inductances were analyzed by the Q3D Extractor and verified by the time-domain reflectometry (TDR) measurements. In most cases, the TDR measurement results closely matched those predicted by the Q3D Extractor. These methods were applied to design and analyze a 50KVA 650V silicon carbide (SiC) half-bridge power electronic power module consisting of three separate power substrates interconnected in parallel. The layout of this power module was constrained by the existing module housing. The parasitic inductances of the power module substrates were measured by TDR, and compared to those simulated values by the Q3D Extractor. Due to the differences in the lengths of current paths, the parasitic circuit elements for the three paralleled SiC power substrates, each consisting of 10 SiC power MOSFETs and 9 SiC diodes, were different.
"],"dc:identifier":["https://scholarworks.uark.edu/etd/858"],"dc:subject":["Applied sciences","Parasitic inductance","Power electronics","Power module","Semiconductor devices","Electrical and Electronics","Electronic Devices and Semiconductor Manufacturing","Power and Energy"],"dc:title":["Electrical Design Considerations and Packaging of Power Electronic Modules"],"thesis:degree_level":["Thesis"],"thesis:degree_name":["Master of Science in Electrical Engineering (MSEE)"]},"updated_at":"2026-07-24T01:00:19Z"}