Comparison of Various Pipelined and Non-Pipelined SCl 8051 ALUs

<p>This paper describes the development of an 8-bit SCL 8051 ALU with two versions: SCL 8051 ALU with <em>nsleep</em> and <em>sleep</em> signals and SCL 8051 ALU without <em>nsleep</em>. Both versions have combinational logic (C/L), registers, and completion components, which all utilize slept gates. Both three-stage pipelined and non-pipelined designs were examined for both versions. The four designs were compared in terms of area, speed, leakage power, average power and energy per operation. The SCL 8051 ALU without <em>nsleep</em> is smaller and faster, but it has greater leakage power. It also has lower average power, and less energy consumption than the SCL 8051 ALU with both <em>nsleep</em> and <em>sleep</em> signals. The pipelined SCL 8051 ALU is bigger, slower, and has larger leakage power, average power and energy consumption than the non-pipelined SCL 8051 ALU.</p>

Name thesis:degree_name

Master of Science in Electrical Engineering (MSEE)

Level thesis:degree_level

Thesis

Year dc:date.available

2012

Author dc:creator

• Zhao, Jingyi

Advisor dc:contributor.advisor

• Smith, Scott C.

Contributors dc:contributor

• Di, Jia
• Brown, Randy L.

• Applied sciences
• Arithmetic Logic Unit
• Pipeline
• Sleep convention logic
• VLSI and Circuits, Embedded and Hardware Systems

Repository record dc:identifier

https://scholarworks.uark.edu/etd/552

OAI identifier oai:identifier

oai:scholarworks.uark.edu:etd-1551