This paper describes the development of an 8-bit SCL 8051 ALU with two versions: SCL 8051 ALU with nsleep and sleep signals and SCL 8051 ALU without nsleep. Both versions have combinational logic (C/L), registers, and completion components, which all utilize slept gates. Both three-stage pipelined and non-pipelined designs were examined for both versions. The four designs were compared in terms of area, speed, leakage power, average power and energy per operation. The SCL 8051 ALU without nsleep is smaller and faster, but it has greater leakage power. It also has lower average power, and less energy consumption than the SCL 8051 ALU with both nsleep and sleep signals. The pipelined SCL 8051 ALU is bigger, slower, and has larger leakage power, average power and energy consumption than the non-pipelined SCL 8051 ALU.
","abstract_html":"<p>This paper describes the development of an 8-bit SCL 8051 ALU with two versions: SCL 8051 ALU with <em>nsleep</em> and <em>sleep</em> signals and SCL 8051 ALU without <em>nsleep</em>. Both versions have combinational logic (C/L), registers, and completion components, which all utilize slept gates. Both three-stage pipelined and non-pipelined designs were examined for both versions. The four designs were compared in terms of area, speed, leakage power, average power and energy per operation. The SCL 8051 ALU without <em>nsleep</em> is smaller and faster, but it has greater leakage power. It also has lower average power, and less energy consumption than the SCL 8051 ALU with both <em>nsleep</em> and <em>sleep</em> signals. The pipelined SCL 8051 ALU is bigger, slower, and has larger leakage power, average power and energy consumption than the non-pipelined SCL 8051 ALU.</p>","abstract_has_math":false,"creators":["Zhao, Jingyi"],"institution":null,"degree_name":"Master of Science in Electrical Engineering (MSEE)","degree_level":"Thesis","degree_discipline":null,"degree_department":null,"school":null,"contributors":["Di, Jia","Brown, Randy L."],"advisors":["Smith, Scott C."],"committee_chairs":[],"committee_members":[],"year":2012,"date_issued":"2012-08-01T07:00:00Z","date_published":"2012-08-01T07:00:00Z","updated_at":"2026-07-24T00:59:01Z","subjects":["Applied sciences","Arithmetic Logic Unit","Pipeline","Sleep convention logic","VLSI and Circuits, Embedded and Hardware Systems"],"languages":[],"rights":[],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://scholarworks.uark.edu/etd/552","outbound_label":"Repository record","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Di, Jia","Brown, Randy L."]},{"key":"dc:contributor.advisor","label":"Advisor","values":["Smith, Scott C."]},{"key":"dc:creator","label":"Author","values":["Zhao, Jingyi"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2012"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2017-09-29T07:00:00Z"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Master of Science in Electrical Engineering (MSEE)"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Applied sciences","Arithmetic Logic Unit","Pipeline","Sleep convention logic","VLSI and Circuits, Embedded and Hardware Systems"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://scholarworks.uark.edu/etd/552"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["This paper describes the development of an 8-bit SCL 8051 ALU with two versions: SCL 8051 ALU with nsleep and sleep signals and SCL 8051 ALU without nsleep. Both versions have combinational logic (C/L), registers, and completion components, which all utilize slept gates. Both three-stage pipelined and non-pipelined designs were examined for both versions. The four designs were compared in terms of area, speed, leakage power, average power and energy per operation. The SCL 8051 ALU without nsleep is smaller and faster, but it has greater leakage power. It also has lower average power, and less energy consumption than the SCL 8051 ALU with both nsleep and sleep signals. The pipelined SCL 8051 ALU is bigger, slower, and has larger leakage power, average power and energy consumption than the non-pipelined SCL 8051 ALU.
"]},{"key":"dc:title","label":"Title","values":["Comparison of Various Pipelined and Non-Pipelined SCl 8051 ALUs"]}]}],"canonical_facts":{"dc:contributor":["Di, Jia","Brown, Randy L."],"dc:contributor.advisor":["Smith, Scott C."],"dc:creator":["Zhao, Jingyi"],"dc:date":["2012"],"dc:date.available":["2017-09-29T07:00:00Z"],"dc:description.abstract":["This paper describes the development of an 8-bit SCL 8051 ALU with two versions: SCL 8051 ALU with nsleep and sleep signals and SCL 8051 ALU without nsleep. Both versions have combinational logic (C/L), registers, and completion components, which all utilize slept gates. Both three-stage pipelined and non-pipelined designs were examined for both versions. The four designs were compared in terms of area, speed, leakage power, average power and energy per operation. The SCL 8051 ALU without nsleep is smaller and faster, but it has greater leakage power. It also has lower average power, and less energy consumption than the SCL 8051 ALU with both nsleep and sleep signals. The pipelined SCL 8051 ALU is bigger, slower, and has larger leakage power, average power and energy consumption than the non-pipelined SCL 8051 ALU.
"],"dc:identifier":["https://scholarworks.uark.edu/etd/552"],"dc:subject":["Applied sciences","Arithmetic Logic Unit","Pipeline","Sleep convention logic","VLSI and Circuits, Embedded and Hardware Systems"],"dc:title":["Comparison of Various Pipelined and Non-Pipelined SCl 8051 ALUs"],"thesis:degree_level":["Thesis"],"thesis:degree_name":["Master of Science in Electrical Engineering (MSEE)"]},"updated_at":"2026-07-24T00:59:01Z"}