Publikationsserver der RWTH Aachen University
Design and analysis of future memories based on switchable resistive elements
Abstract
dc:descriptionResistive bistable thin film elements have a great potential for implementing non-volatile memories with extreme densities. This work investigates using the switching characteristics of these resistive switchable elements to implement active and passive memory arrays. First, different active memory architectures has been investigated analytically and numerically based on the resistive elements which are characterised through there hysteretic resistive I/V curve. A new active memory cell concept which uses a capacitor connected serially to the resistive element has been proposed as an alternative the conventional memory cell. This concept simplifies the manufacturing of the memory and makes it possible to generate a higher voltage than the supply voltage across the resistive elements. Passive memory architectures based on crossbar-arrays are very compact because they don’t include a transistor in the memory cells. Different active periphery circuits for the read and write operations has been elaborated. In the case of the write operation, the periphery circuits generate more than two voltage levels to accomplish writing. The read and write operations for passive resistive memories has been discussed thoroughly. It has been shown that many simplifications which have been used when analysing passive memories don’t work under real conditions. This is especially true when the interconnect resistances are considered. The optimal array sizes and optimal values of the sense resistors are calculated depending on the memory array parameters like the on- and off-resistance values of the memory cell and the interconnects resistance values. When the interconnect resistances are considered the voltages at the memory cells and the sense resistors are degraded. This degradation limits the construction of large memory arrays. Due to the voltage degradation at the sense resistors, the memory cells can not be read correctly because a common reference voltage does not consider this degradation. To solve this problem, a new concept for the generation of the reference voltage has been proposed. This concept uses dedicated memory cells to generate local and reliable reference voltages, which enables the construction of larger memory arrays. Resistive memory arrays with an additional diode in the memory cells have also been discussed. The usage of a diode reduces the parasitic effects and also allows the construction of larger memory arrays. Finally, the usage of resistive memory elements in lookup tables of FPGAs has been investigated. A simplified write operation which functions under certain conditions has been proposed. In addition, a rule that directly specifies the worst case patterns has been found. By using this rule, long simulation times to find these patterns are avoided.
Degree
thesis:*- Grantor dc:publisher
- Publikationsserver der RWTH Aachen University
- Year dc:date
- 2006
Author and committee
dc:creator, dc:contributor.*- Author dc:creator
-
- Mustafa, Jakob
- Contributors dc:contributor
-
- Waser, Rainer
Subjects
dc:subject × 7Rights
dc:rights- Statement dc:rights
-
- info:eu-repo/semantics/openAccess
- Language dc:language
- eng