Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 46 for “"Crossbar"”.
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Design and analysis of memristor-based reliable crossbar architectures
… the sneak-paths current which limits the maximum crossbar array size. This thesis presents various designs of the memristor based crossbar architecture and corresponding experimental analysis towards addressing its reliability issues. Novel contribution of this thesis starts with the formulation …
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Carbon nanotube crossbar electrodes for high performance memory devices
Item marked as restricted to the 'Administrator' Group (id=1) by Seth Robbins (srobbins@illinois.edu) on 2013-08-22T16:57:35Z Item is restricted until 2015-08-22T16:57:26Z
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Providing QoS guarantees in input buffered crossbar switches with speedup
… Quality of Service guarantees in input-buffered crossbar switches with speedup. It is shown that speedup of 4 is sufficient to ensure 100% asymptotic throughput with any maximal matching algorithm employed by the arbiter. It is also demonstrated that the crossbar architecture is capable of …
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Architecture design and performance analysis of practical buffered-crossbar packet switches
… However, the amount of memory required in the crossbar of an N x N switch is N^2x k x L, where k is the crosspoint buffer size and needs to be of size RTT in cells, L is the packet size. RTT is the round-trip time which is defined by the distance between line cards and switch fabric. When the …
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CHARACTERIZATION OF SNEAK PATH CURRENT EFFECT IN A PEDOT: PSS-BASED ReRAM CROSSBAR ARRAY
… characterization of resistive switching memory crossbar devices fabricated on glass substrates with a structure of Cu/PEDOT: PSS/Ag, with a particular focus on understanding the impact of sneak-path currents on the switching performances. Resistive memory cells, particularly in crossbar …
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Design of the interconnection network for the EARTH system
… network consists of a hierarchy of 4 x 4 crossbar switches, and a network interface on each EARTH processor node. The interconnection network is capable of transferring multiple messages simultaneously between nodes. The interconnection network also supports random routing that allows the …
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Low-swing signaling for energy efficient on-chip networks
… an ideal interconnection fabric. A low-swing crossbar switch, which is based on tri-state Reduced-Swing Drivers (RSDs), is presented for the first project. Measurement results of its test chip fabricated in 45nm SOI CMOS show that the tri-state RSD-based crossbar enables 55% power savings as …
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Network coding for speedup in switches
… it is known that linear network coding in a crossbar switch can sustain traffic patterns that cannot be served if network coding were not allowed. Thus, network coding leads to a larger rate region in a multicast crossbar switch. This thesis quantities the gain in rate region in a multicast …
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A Reconfigurable FPGA Overlay Architecture for Matrix-Matrix Multiplication
… systolic architectures is a multiplexer-based crossbar network that interconnects every processing element in the network. The crossbar network grants user run-time reconfigurability of the topology of the systolic array, enabling the user to specify the shape and size of the systolic …
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A Universal Heterostructure for Photonic Integrated Circuit Applications
… circuits are investigated using an optical 2 x 2 crossbar switch as a case study. The optical characteristics of slab waveguides are investigated as candidate "universal" structures. Different core profiles, core sizes, and cladding arrangements are considered. A reverse-biased laser …
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Design, Analysis and Testing of Efficient Memristive Neural Networks
… various single and multi-layer memristive crossbar neural architectures are implemented and tested in SPICE. Experimental results show that this learning method performed e ciently while implementing memristor-based neural networks in ex-situ. The results also demonstrated that the …
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Analog On-chip Training and Inference with Non-volatile Memory Devices
… devices. These devices are structured into crossbar arrays. To explore the potential of non-volatile memory devices in AIMC, investigations involve simulating crossbar array operations using IBM’s AIHWKIT. With this tool, I investigate the implementation of various analog computing …
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Integrated Photonic Iterative Processors for Computing
… The first 2×2 and 4×4 partially integrated crossbar array-based PIPs for real-valued matrix inversions are demonstrated experimentally. The 4×4 partially integrated crossbar array-based PIP is also used to solve integral and differential equations involving 8×8 and 16×16 matrix inversions by …
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Contribución al estudio y desarrollo de arquitecturas para interconexionado óptico de señales y reconocimiento de imágenes
… The second system demonstrates an acousto-optic crossbar switching network. The 12 £ 12 crossbar switch is supported by a complete 1.2 Gb/s ¯ber-optic switching testbed with integral computer control from a single la- boratory PC. The last system describes a ¯ber-based image transmission …
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Network-on-chip design for a chiplet-based waferscale processor
… architectural change is the shift from bus and crossbar based processor interconnections to networks-on-chip (NoCs). This thesis details the design of an NoC to enable a shared memory architecture in a chiplet-based wafer scale processor with architectural support for up to 14,336 cores.
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Memristor-based AI Hardware for Reliable and Reconfigurable Neuromorphic Computing
… that works dependably and enables large-scale crossbar array deployment. In addition, heterogeneously integrated neuromorphic chips have been developed to allow physically reconfigurable neuromorphic computing. This thesis examines alloyed metal-based silicon memristors and stackable …
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Large-scale neuromorphic computing hardware for analog AI enabled by epitaxial random access memory
A neuromorphic computing on memristor-based crossbars is one of promising next generation analog computing methods since it features fast switching speed, extremely small cell footprint, low energy consumption for matrix-vector multiplication, capability of both storage and computing, …
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Design and stability analysis of high performance packet switches
… the crosspoint buffer size. As the buffered crossbar switch can be physically located far from the input ports, actual round-trip times can be non-negligible. To support non-negligible round-trip times in a buffered crossbar switch, the crosspoint buffer size needs to be increased. To satisfy …
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Adaptive digital multiprocessor systems for image processing applications
… are discussed, and a brief comparison of crossbar, multiple bus and partial bus interconnection networks is presented. The redundancy in the partial bus is discussed and a new interconnection network is proposed. Chapter 4 outlines the design, construction and testing of arbitration, …
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The Folded Hypercube ATM Switches
… fabric for the first time instead of using the crossbar, multi-path, or Banyan-based switching fabrics.
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