Publikationsserver der RWTH Aachen University
Language-driven exploration and implementation of partially re-configurable ASIPs (rASIPs)
Abstract
dc:descriptionBackground: In today’s embedded processors, performance and flexibility have become two key attributes. These attributes are often conflicting. The best performance is obtained from custom designed integrated circuits. In contrast, the maximum flexibility is delivered by a general purpose processor. Among the architecture types emerged over the past years to strike an optimum balance between these two attributes, two are prominent. The first ones are Field Programmable Gate Array (FPGA)-based architectures and the second ones are Application-Specific Instruction-set Processors (ASIPs). Depending on the type of application (i.e. stream-like or control-dominated) either one of the aforementioned architecture types is able to deliver high performance or flexibility or both. Consequently, a novel class of processor architectures combining FPGA and ASIP, is currently an active area of research. The design space of partially re-configurable ASIPs (rASIPs) is complex and huge. The design space consists of three overlapping sub-spaces namely, ASIP design, FPGA design and the interface design. Currently, ADL LISA is extensively used for modelling ASIPs. However, the lack of a complete rASIP modelling framework restricted most of the early rASIP designers to remain limited within a few design decisions. The biggest challenges in this task was identified to be firstly, allowing arbitrary design partitions in high-level of abstraction and secondly, seamlessly integrating two paradigms of synthesis flow i.e. ASIC and FPGA in one design framework. To address this challenges, in this thesis, a generic rASIP modelling, exploration and implementation flow is presented. Language-driven rASIP Exploration and Implementation: The work presented in this thesis begins with the identification of a broad range of possible design choices in the field of partially re-configurable processor design. Thenceforth, the design flow is segmented into two subsequent phases namely, pre-fabrication phase and post-fabrication phase. At this point, the exact requirements of design tools are noted. To facilitate fast design space exploration and convenient modelling - a suitable, generic language-driven platform for ASIP design (CoWare/LISATek) is chosen as the basis. The language LISA is extended with new features to enable the modelling of the entire partially re-configurable processor. The exact steps in the two design phases are as following. Pre-fabrication Design Flow: This phase of design happens before the rASIP is fabricated. The design decisions considering the interplay among them are taken without any further restrictions at this phase. Finally, the design is implemented partially on fixed and partially on re-configurable hardware. The interface between the processor and the re-configurable part is inferred and stored. Post-fabrication Design Flow: This phase of design happens after the rASIP is fabricated. In this phase, the base processor and the interface between the processor and the re-configurable block is fixed. Therefore, the architecture design space is limited to the possible configurations of the re-configurable block only. Both the design phases use the same tool flow. At the beginning, the application is profiled followed by a manual development of the complete rASIP description using extended LISA. From the rASIP description, software tools as well as hardware implementation are automatically generated. The hardware implementation is partly (as per designer’s specification) re-directed to the coarse-grained FPGA synthesis flow to generate configuration bitstream. The entire rASIP is then simulated in RT-level - feeding the detailed performance analysis back to co-explore the application and architecture alternatives. As proof-of-concept of the proposed design flow, several case studies with embedded and multimedia benchmarks have been performed. To show the use-case of rASIP, a CDMA-based wireless receiver protocol is chosen. It is shown that for the CDMA implementation, various constraints of flexibility and performance are to be met - which can be handled by rASIPs. To fine tune the balance between performance and flexibility, joint exploration of the complete architecture i.e. FPGA and the base processor is essential, as proposed in this thesis. Continued interest on this topic depends heavily on the blending of heterogeneous applications into a single system, which is the current trend. Further research on the rASIP design flow need to focus on such evolving and merging application scenario such as software defined radio.
Degree
thesis:*- Grantor dc:publisher
- Publikationsserver der RWTH Aachen University
- Year dc:date
- 2008
Author and committee
dc:creator, dc:contributor.*- Author dc:creator
-
- Chattopadhyay, Anupam
- Contributors dc:contributor
-
- Meyr, Heinrich
- Ascheid, Gerd
- Ienne, Paolo
Subjects
dc:subject × 6Rights
dc:rights- Statement dc:rights
-
- info:eu-repo/semantics/openAccess
- Language dc:language
- eng