Global ETD Search

A reconfigurable systolic array architecture for multicarrier wireless applications

Ho, HuongCarleton University2009

carleton Repository record for A reconfigurable systolic array architecture for multicarrier wireless applications (opens in a new tab)

A VLSI systolic array processor for complex singular value decomposition

Niessen, Christopher CharlesMassachusetts Institute of Technology1994

… of achieving the maximum possible performance, a systolic array processor for computing the singular value decomposition of an arbitrary complex matrix was designed using a silicon compiler system. This system allows for ease of design by specification of the processor architecture in a high level …

mit Repository record for A VLSI systolic array processor for complex singular value decomposition (opens in a new tab)

A comparative study of synchronous and self-timed systolic array architectures.

Hogg, R. S.Sheffield Hallam University (United Kingdom).1997

This thesis examines systolic array architectures and their methods of control and communication synchronisation. Systolic array processors suffer from synchronisation problems associated with the clocking mechanism that causally restricts their scalability. To overcome this problem both …

sheffield-hallam Repository record for A comparative study of synchronous and self-timed systolic array architectures. (opens in a new tab)

Efficient exploration of affine space-time transformations for optimal systolic array synthesis

Baltus, Donald GeorgeMassachusetts Institute of Technology1994

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.

mit Repository record for Efficient exploration of affine space-time transformations for optimal systolic array synthesis (opens in a new tab)

Dynamically Reconfigurable Systolic Array Accelerators: A Case Study with Extended Kalman Filter and Discrete Wavelet Transform Algorithms

Barnes, Robert C

utahstate Repository record for Dynamically Reconfigurable Systolic Array Accelerators: A Case Study with Extended Kalman Filter and Discrete Wavelet Transform Algorithms (opens in a new tab)

A pipelined array architecture for motion estimation in H.264/AVC and mapping multiple algorithms into a reconfigurable systolic array.

Jin, WeiFaculty of Graduate Studies and Research, University of Regina2008

regina Repository record for A pipelined array architecture for motion estimation in H.264/AVC and mapping multiple algorithms into a reconfigurable systolic array. (opens in a new tab)

Design and implementation of a systolic array to solve the Algebraic Path Problem with the specific instance of the transistive and reflexive closure of a binary relation

McCall, David Gene

rit Repository record for Design and implementation of a systolic array to solve the Algebraic Path Problem with the specific instance of the transistive and reflexive closure of a binary relation (opens in a new tab)

Efficient Architecture and Implementation for NTRU Based Systems

Liu, BingxinUniversity of Windsor2015

… modest increase of the complexity. Thirdly, a systolic array architecture is proposed for NTRUEncrypt. There is only one type of PE (process element) in the array and the PE was designed with optimized arithmetic. The systolic array yields all the output in N clock cycles. Two new architectures …

windsor Repository record for Efficient Architecture and Implementation for NTRU Based Systems (opens in a new tab)

Smart IP of QR decomposition for rapid prototyping on FPGAs

Saqib, SunilaMassachusetts Institute of Technology2014

… Our QRD design based on a Log-domain GR Systolic array achieved a throughput of 10.1M rows/sec for a complex valued 3x3 matrix on Virtex-6 FPGA, whereas our QRD design based on a Log-domain GR Linear array was found to be an area optimized solution requiring the fewest FPGA slices. …

mit Repository record for Smart IP of QR decomposition for rapid prototyping on FPGAs (opens in a new tab)

Architectural, numerical and implementation issues in the VLSI design of an integrated CORDIC-SVD processor

Kota, KishoreRice University1991

This thesis describes the design of a systolic array for computing the Singular Value Decomposition (SVD) based on the Brent, Luk, Van Loan array. The use of COordinate Rotation DIgital Computer (CORDIC) arithmetic results in an efficient VLSI implementation of the processor that forms the basic …

rice Repository record for Architectural, numerical and implementation issues in the VLSI design of an integrated CORDIC-SVD processor (opens in a new tab)

A Reconfigurable FPGA Overlay Architecture for Matrix-Matrix Multiplication

Chen, Zihao2022

… circuits (ASICs), and field-programmable arrays (FPGAs) are used for this purpose. However, a trade-off between the two platforms is that ASICs provide little flexibility after they are manufactured while designs on FPGAs are flexible but application development on FPGAs is more …

wustl Repository record for A Reconfigurable FPGA Overlay Architecture for Matrix-Matrix Multiplication (opens in a new tab)

C-Flow : a compiler for statically scheduled message passing in parallel programs

Griffin, Patrick (Patrick Robert)Massachusetts Institute of Technology2005

… parallelism is possible because, as in systolic array machines, the network provides all of the necessary synchronization between tiles. On the Raw processor, C-Flow reduces development complexity by allowing the programmer to schedule static messages from a high-level language instead …

mit Repository record for C-Flow : a compiler for statically scheduled message passing in parallel programs (opens in a new tab)

Delocalized Photonic Deep Learning on the Internet's Edge

Sludds, AlexanderMassachusetts Institute of Technology2023

… all non-local metallic wires in a digital systolic array with free-space optical interconnections enabled by fan-out and receiverless photodetectors. For the primary contribution of my thesis I explore making use of photonics to enable faster edge computing. Advanced machine learning models …

mit Repository record for Delocalized Photonic Deep Learning on the Internet's Edge (opens in a new tab)

Large-Scale Optical Hardware for Neural Network Inference Acceleration

Bernstein, LianeMassachusetts Institute of Technology2024

… but not in tightly packed electronic multiplier arrays. Therefore, in a second project, we expanded upon this work by performing reconfigurable optical multicast and analog optoelectronic weighting to compute DNN layer outputs in a single shot. Our proof-of-concept system yielded an MNIST …

mit Repository record for Large-Scale Optical Hardware for Neural Network Inference Acceleration (opens in a new tab)

Parallelization of dynamic programming recurrences in computational biology

Jacob, Arpith2010

… kernels using field-programmable gate arrays: FPGAs). We advocate a high-level synthesis approach, using the recurrence equation abstraction to represent dynamic programming and polyhedral analysis to exploit parallelism. We suggest a novel technique within the polyhedral model to …

wustl Repository record for Parallelization of dynamic programming recurrences in computational biology (opens in a new tab)

From TPU to QPU: Bridging Fidelity Gaps Across Next-Generation Computing Systems

Charrwi, Mohammad Walid M2025

<p>Modern computing systems continue to advance rapidly, enabling unprecedented computational capabilities across diverse domains. Among these powerful architectures are AI accelerators such as Tensor Processing Units (TPUs) and quantum computing systems utilizing Quantum Processing Units (QPUs) …

cuny Repository record for From TPU to QPU: Bridging Fidelity Gaps Across Next-Generation Computing Systems (opens in a new tab)