Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 21 for “"post-silicon"”.
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Protocol-directed trace signal selection for post-silicon validation
… using NoC (network-on-chip) communication, post-silicon validation has become an arduous task that consumes much of the development time of the product. The process of finding the root cause of bugs during post-silicon validation is very difficult because of the lack of observability of all …
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System-level trace signal selection for post-silicon debug using linear programming
… using NoC (network- on-chip) communication, post-silicon validation has become and arduous task that consumes much of the development time of the product. The process of finding the root cause of bugs found in post-silicon validation has proven to be much more difficult than in pre-silicon …
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High quality functional coverage based trace signal selection for post-silicon validation
… impossible to capture all bugs during the pre-silicon verification phase; therefore, a small number of bugs escape after a chip is manufactured. Once a chip is manufactured, it is considered as a black box since internal observability is lost. To increase observability for post-silicon …
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Novel Architectures for Trace Buffer Design to facilitate Post-Silicon Validation and Test
Post-Silicon validation is playing an increasingly important role as more chips are failing in the functional mode due to either manufacturing defects escaped during scan-based tests or design bugs missed during pre-silicon validation. Critical to the diagnosis engineer is the ability to observe as …
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Atomic-scale engineering of 2D materials via scanning tunneling microscopy: Bridging synthesis, characterization, and device integration for post-silicon electronics
Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2027-05-01
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Non-invasive IC tomography using spatial correlations
We introduce a new methodology for post-silicon characterization of the gate-level variations in a manufactured Integrated Circuit (IC). The estimated characteristics are based on the power and the delay measurements that are affected by the process variations. The power (delay) variations are …
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Scalable functional validation of next generation SoCs
… This dissertation makes contributions to both post-silicon and pre-silicon validation of SoCs, with highly impactful contributions to next-generation post-silicon SoC validation. We use top-down analysis, a higher level of abstraction, and application relevance as the key ideas to automate …
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Algorithms and Low Cost Architectures for Trace Buffer-Based Silicon Debug
An effective silicon debug technique uses a trace buffer to monitor and capture a portion of the circuit response during its functional, post-silicon operation. Due to the limited space of the available trace buffer, selection of the critical trace signals plays an important role in both minimizing …
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Energy-Efficient and Error-Tolerant Digital Design
… to extending Moore's law into the deep nanoscale silicon and post-silicon era.
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Testing and Verification Strategies for Enhancing Trust in Third Party IPs
… to test portions of the design testable at the post silicon stage. We propose two different approaches to enhance the testability of the overall circuit. The first allows improved at-speed testing for the design while the second aims to exaggerate the effect of unwanted tampering (if present) on …
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Low-cost error detection through high-level synthesis
… against soft errors. Another solution for rapid post-silicon validation of accelerator designs is Hybrid Quick Error Detection (H-QED): inserting signature generation logic in a hardware design to create a heavily compressed signature stream that captures the internal behavior of the design at a …
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PARALLEL DELAY FAULT GRADING HEURISTIC AND TESTING APPROACHES TO TROJAN IC DETECTION
… and can be shown to scale to multiple GPGPUs. A post-silicon test pattern generation strategy to maximize the efficiency of broadside tests applied to a sequential design for a limited test budget is presented. Arguments are made for this approach for detecting embedded Trojan ICs in the …
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Probing two-dimensional magnetic phenomena with diamond quantum microscopy
… and character- isation of novel materials for post-silicon technology. The development of high-density memory devices based on novel magnetic materials has promising aspects such as un- matched data retention and low power consumption. However, this technology is still in its early stages and …
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Smart Systems Based on Electroactive Polymers
… electronics, opening new possibilities for a post-silicon era. Characteristics like the large deformations obtained under the ef-fect of a low level applied voltage signal, the capability to transform a mechanical stimulus into a detectable electrical signal and the vibra-tional …
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Synthesis of 1T-Tantalum (IV) Sulfide and observation of charge density wave using scanning tunneling microscopy
… in finding an alternate material system for post-silicon logic and opto-electronic applications, staggering progress have been made in the study of low-dimensional materials. These low-dimensional materials not only help reduce transistor footprint and improve power and performance metrics, …
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Branch Guided Metrics for Functional and Gate-level Testing
… at different levels of abstraction such as post-silicon validation. Experimental results show that use of the new metric in our test generation framework can achieve a high level of branch and fault coverage for several benchmark circuits, while reducing the length of the vector sequence. …
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Robust and reliable hardware accelerator design through high-level synthesis
… stages in the hardware design and use cycle: pre-silicon debugging, post-silicon validation, and post-deployment error detection. Our solution for rapid pre-silicon debugging of accelerator designs is hybrid tracing: comparing a datapath-level trace of hardware execution with a reference software …
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A truly embedded test structure for design-for-manufacturability, hardware security and VLSI testing
… in several contexts including defect detection, post-silicon debug and hardware-security. In this dissertation, I propose a high-precision and low-overhead embedded test structure, called REBEL, for measuring path delays in the circuit context. REBEL is minimally invasive to the design, as it …
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Theoretical Study of Carbon-Based Materials and Their Applications in Nanoelectronics
Continual scaling down of silicon device, which is the main driving force in device performance enhancement, is not sustainable as we approach the physical limits of silicon and it is foreseen that new materials and novel device structures will be required for future device improvements. In this …
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