Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 9 of 9 for “"logic optimization"”.
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Logic optimization of MOS networks
The logic networks that can be put on a single chip continues to grow in size and complexity. There is thus an increasing need for designers to rely on the assistance of computer-aided design tools to provide a fast design turnaround and reduce design errors. Logic design (or logic synthesis) is …
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A system for microarchitecture and logic optimization
… the design of numerous behavioral synthesis and logic synthesis tools. This thesis spans two levels of the design process by examining optimization at both the register-transfer level and at the logic level. More specifically, this thesis addresses the following two problems: (1) performing logic …
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Precomputation-based sequential logic optimization for low power
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.
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Analysis and optimization of digital circuit dynamic behavior
… analytical timing-error-probability framework, a logic optimization algorithm is developed to utilize dual threshold voltage (dualVt) cells to optimize a circuit's throughput in such a way that the most dynamically critical gates of a circuit can be identified and optimized. To make the …
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Static Learning for Problems in VLSI Test and Verification
Static learning in the form of logic implications captures Boolean relationships between various gates in a circuit. In the past, logic implications have been applied in several areas of electronic design automation (EDA) including: test-pattern-generation, logic and fault simulation, fault …
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Reliable chip design from low powered unreliable components
The pace of technological improvement of the semiconductor market is driven by Moore’s Law, enabling chip transistor density to double every two years. The transistors would continue to decline in cost and size but increase in power. The continuous transistor scaling and extremely lower power …
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Toward high-level synthesis of reliable circuits through low-cost modulo shadow datapaths
… and modulo-b reducer sharing. We introduce logic and dataflow optimizations to further reduce cost. We evaluated our technique with 12 high-level synthesis benchmarks from the arithmetic- oriented PolyBench benchmark suite using FPGA emulated netlist-level error injection. When b = 3, we …
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Low-cost error detection through high-level synthesis
… reliability and validation challenges including logic bugs, hot spots, wear-out, and soft errors. To make matters worse, as we reach the limits of Dennard scaling, efforts to improve system performance and energy efficiency have resulted in the integration of a wide variety of complex hardware …
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Robust and reliable hardware accelerator design through high-level synthesis
… reliability and validation challenges including logic bugs, hot spots, wear-out, and soft errors. To make matters worse, as we reach the limits of Dennard scaling, efforts to improve system performance and energy efficiency have resulted in the integration of a wide variety of complex hardware …