Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 17 of 17 for “"double gate"”.
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Fabrication technology for double-gate field effect transistors
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1999.
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Performance Analysis of Double Gate MOSFET Using Monte Carlo Simulation
… speci cally the drain current drive, of the double gate silicon MOSFET device, using MoCa, the Monte Carlo simulator. Drain current performance is analyzed as a result of varying di erent parameters like oxide thickness, dielectric constant, and misalignment of top and bottom gates. An …
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Development and Characterization of Flexible Double-Gate Organic Transistors for Sensing Applications
… of use, and advantages that offers. The double-gate architecture, both in inorganic and organic electronics, is vastly used and studied, as it presents itself as a platform for the realization of versatile devices, from circuitry to sensing. As a matter of fact, as will also be presented …
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X-ray lithographic alignment and overlay applied to double-gate MOSFET fabrication
Double-gate MOSFETs represent a significant solution to transistor scaling problems and promise a dramatic improvement in both performance and power consumption. In this work, a planar lithographic process is presented that is capable of producing double-gate MOSFET (DGFET) gate structures with 50 …
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A comparison of electrical performance analysis between nanoscale double-gate and gate-all-around nanowire mosfet
The Double-Gate and Gate-all-Around are said to be the promising candidates to pursue Complementary-Metal-Oxide Semiconductor scaling. When the device is scaled down, several problems arise such as the short-channel effect, excessive transistor gate leakage and power consumption. The purpose of …
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Monte Carlo simulation for high-frequency intrinsic noise analysis of MOSFET
… our device into noise two-port model. A 30 nm double gate FinFET is chosen as a simulation model and the intrinsic noise of the device is examined. As a result, the double gate FinFET showed lower gate and source access resistance, and minimum noise figure, which contains important information …
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Toward the end of the MOSFET roadmap : investigating fundamental transport limits and device architecture alternatives
… rapidly in recent years, with physical gate lengths for electrostatically sound devices reaching 30 nm or below: near the prospective scaling limits for traditional bulk MOSFETs. This work investigates several key issues for this "end of roadmap" regime. Focus is on understanding the …
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Electronic devices based on semiconducting transition metal dichalcogenides
… bonds and tunable bandgaps. This thesis investigates various transistors based on exfoliated and synthesized TMD materials. As a base for the results reported in this thesis, the fabrication processes are developed with key steps and parameters presented in detail. The characterization methods …
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Device design and process technology for sub-100 nm SOI MOSFET's
… to bulk-silicon MOSFET's in the sub-100 nm gate length regime due to improved performance and/or scalability. The SOI layer thickness in SOI MOSFET's can be sized so that the channel is either partially- or fully-depleted-of majority carriers. Partially-depleted (PD) SOI MOSFET's are easier …
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Tunneling Field-Effect Transistors for Low Power Logic: Design, Simulation and Technology Demonstration
… field-effect transistor (MOSFET). TFET exploits gate modulated band-to-band tunneling (BTBT) to achieve a steep S and a high on-state current Ion to off-state current Ioff ratio at a low supply voltage VDD. However, current TFET technology is still under development, and most reported TFETs …
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Design-technology Co-optimization for Sub-2 nm Technology Node Based on 2D Materials
… of DTCO, we have achieved record performance for double-gate, single-channel MoS₂ transistors as well as the first demonstration of high-performance, functional double channel MoS₂ transistors. Based on the results of MCTs, a Process Design Kit (PDK) is developed to facilitate circuit-level …
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The Design of an Asic Control Chip for a Forward Active Clamp Converter and the Investigation of Integratable Lateral Power Devices
… including lateral IGBT, lateral MCT and double gate lateral MCTs. It is shown that lateral IGBT and lateral MCTs are good candidates for power IC applications.
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The effects of strain on carrier transport in thin and ultra-thin SOI MOSFETs
… MOSFET geometries such as fully-depleted SOI and double-gate devices are attractive because they can offer superior scaling properties compared to bulk and thick-body SOI devices. The electrostatics of a MOSFET limit how short of a gate length can be achieved before the gate loses control over the …
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Micromachining and modeling of focused field emitters for flat panel displays
… field emitter with integrated focus (IFE-FEA) or double-gate FEA (DG-FEA). The main application of IFE-FEA is to improve the resolution of field emission displays (FEDs). We developed the first analytical model of conical field emitters that captures all details of device geometry and produces …
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Study of silicon-on-insulator multiple-gate MOS structures including band-gap engineering and self heating effects
… states that the transistors density on chip doubles every 24 months. This trend has been possible due to the downsizing of the MOSFET dimensions (scaling); however, new issues and new challenges are arising, and the conventional ”bulk” architecture is becoming inadequate in order to face …
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Multi-functional Hybrid Gating Silicon Nanowire Field-effect Transistors
… transistors modulated by the stimuli-dependent gate to go beyond the current digital building blocks. The hybrid devices converge semiconductor channel and various materials from organic molecules to silicate composite as a gate of the transistor. External stimuli change the electronic state of …