Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 28 for “"device scaling"”.
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Modeling the effects of device scaling on field emitter array performance
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1996.
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Cryogenic operation of silicon-germanium heterojunction bipolar transistors and its relation to scaling and optimization
… at cryogenic temperatures and its relation to device scaling and optimization. Not only is cryogenic operation of these devices required by space missions, but characterizing their cryogenic behavior also helps to investigate the performance limits of SiGe HBTs and provides essential …
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Protein-mediated nanocrystal assembly for floating gate flash memory fabrication
As semiconductor device scaling is reaching the 45 nm node, the need for novel device concept, architecture and new materials has never been so pressing as today. Flash memories, the driving force of semiconductor memory market in recent years, also face the same or maybe more severe challenges to …
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Submicron Scaling in Indium Phosphide/indium Gallium Arsenide Single Heterojunction Bipolar Transistors
… and detailed understanding of do and RF scaling properties was developed. Important scaling phenomena that emerge as the emitter width is scaled to the deep submicron regime were identified and analyzed. A unique small-signal model extraction procedure was developed and used to study base …
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Heterogeneously Integrated Impedance Based Biosensors
… was performed, and the impact of technology scaling on low-noise transimpedance amplifiers was studied using the Enz-Krummenacher-Vittoz (EKV) model. It was found that the noise performance improves slowly with device scaling down to 90 nm. Further device scaling may increase the gate leakage …
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Development of high-speed P-i-N photodetector for 50Gb/s optical link in data centers
… operating at 50Gb/s. The material structure and device scaling are determined through microwave analysis and simulation. Photodiodes of 20um aperture diameter is fabricated and subsequently characterized, showing both high bandwidth and low noise level. A small signal model is also proposed in …
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System-Technology Co-Optimization of Scaled Electronics Based on Two-Dimensional Materials
… focused on developing highly scaled electronic devices and high-density integrated circuits. However, bottlenecks have arisen recently as transistor dimensions approach the physical limits, and integration density is constrained. This thesis addresses these issues with two-dimensional (2D) …
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Transport in thin-body MOSFETs fabricated in strained Si and strained Si/SiGe heterostructures on insulator
… as strain engineering, with non-classical MOS device architectures, such as ultra-thin body or multiple-gate structures, offers the promise of maximizing current drive while maintaining the electrostatic control required for aggressive device scaling in future CMOS technology nodes. Two …
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Full-band Monte Carlo simulation of hot electrons in scaled silicon devices
"A full-band Monte Carlo device simulator has been used to study the effects of device scaling on hot electrons in different types of n-channel MOSFETs and flash memory structures. A MOSFET with a single source/drain implant, an LDD MOSFET, an SOI MOSFET, and a MOSFET built on top of a heavily …
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Highly Scaled p-GaN-gate HEMTs for Low Voltage Power Electronics
… cloud computing, and Internet of Things (IoT) devices, underscore the need for more efficient power electronics. In particular, power switches based on wide bandgap semiconductors such as gallium nitride (GaN) have emerged as promising alternatives to traditional silicon devices for low-voltage …
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Advanced engineered substrates for the integration of lattice-mismatched materials with silicon
… be attributed to relatively material-independent device scaling. However, with physical and economic limitations to the continued scaling of such devices appearing on the horizon, it is likely that near-term advances will come from the integration of novel and previously underrepresented …
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Techniques for low-power high-performance ADCs
… improves the accuracy of operation. Power supply scaling enhances power efficiency at low sampling rates much like in digital circuits and widens the conversion frequency range where the ADC operates with highest efficiency. The second design is a high speed time-interleaved (TI) SAR ADC with …
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Droplet IO : programmable droplets for human-material interaction
… in this thesis I discuss how semiconductor device scaling applies to electrowetting for smaller volume droplets and hence miniaturized programmable lab-on-a-chip. Droplet based microfluidics is extensively used in biology and chemistry. In this thesis I describe two novel fluid manipulation …
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Power-efficient high-speed interface circuit techniques
… have become the new challenge to enable the scaling of computing systems, ranging from mobile devices to high-end servers. Demand for aggregate I/O bandwidth has been driven by applications including high-speed ethernet, backplane micro-servers, memory, graphics, chip-to-chip and network …
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BiCMOS technology and some applications in high performance arithmetic structures.
… Issues pertaining to BiCMOS process scalability, device scalability, and process tradeoffs are discussed. Included are such topics as active device scaling, second order effects which become important in scaled technologies, BiCMOS process tradeoffs, and latchup in BiCMOS. Several high performance …
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Design Automation and Evaluation Of Emerging 3D – IC Technology Using Stacked Horizontal Nanowires
… below sub 10nm regime now faces fundamental device scaling and interconnect bottlenecks. These limitations are alternatively addressed through 3-D integration of ICs, where pre-fabricated dies or wafers are stacked in a vertical manner. The existing 3-D ICs can be categorized into multilithic …
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Digitally-Assisted RF IC Design Techniques for Reliable Performance
… industries have competitively scaled down CMOS devices to attain benefits of low cost, high performance, and high integration density in digital integrated circuits. On the other hand, deep scaled technologies inextricably accompany a large process variation, supply voltage scaling, and …
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Artificial Intelligence-Aided Synthesis and Characterization of 2D Materials
… and performance degradation will prevent further device scaling down. To address this challenge, two-dimensional (2D) materials have emerged as promising candidates for next-generation transistors, to maintain the pace of Moore's Law—doubling the number of transistors every 18 months. The …
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Dipole Contact Engineering for Field-Effect Transistors Based on Two-Dimensional Materials
… TMDs can enable aggressive lateral and vertical device scaling, and they can add computing power density and new memory and sensing capabilities via 3D integration. However, several key challenges remain before 2D-channel transistors become commercially viable, including large contact resistances …
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A Technology Platform for Enabling Next-Generation Vacuum Electronic Devices Based on Silicon Field Emitter Arrays
… of solid-state, offer a potential alternative device architecture beyond device scaling. Due to their ballistic transport and higher breakdown field, nanoscale vacuum-channel transistors are expected to show better performance in a wide variety of high-frequency, high-power, or harsh …
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