Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
Results
Showing 1 to 20 of 24 for “"deep sub-micron"”.
-
Cell-based array for deep sub-micron technologies
In this thesis I explore transistor topologies for high density cell-based arrays that allows for dense computation blocks, small memory cells, and strong signal drivers. This involves simulating different circuit types with HSPICE to determine ideal transistor sizes. Using Magic and the results of …
-
Interconnect modeling and optimization in deep sub-micron technologies
Interconnect will be a major bottleneck for deep sub-micron technologies in the years to come. This dissertation addresses the communication aspect from a power consumption and transmission speed perspective. A model for the energy consumption associated with data transmission through deep …
-
Non-stationary transport effects in deep sub-micron channel Si mosfets
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineeing, 1989.
-
Novel CAD Techniques for New Challenges in Deep Sub-Micron VLSI Design
In Chapter 2, we present a floorplanning algorithm for 3-D IC designs, which can effectively reduce interconnect delays. Our algorithm is based on a generalization of the classical 2-D slicing floorplans to 3-D slicing floorplans. A new encoding scheme of slicing floorplans (2-D/3-D) and its …
-
Circuit techniques for subthreshold leakage reduction in a deep sub-micron process
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002.
-
Implementation of delay and power reduction in deep sub-micron buses using coding
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002.
-
Coping With Delays And Hazards In Buses And Random Logic In Deep Sub-Micron
… on a line with one adjacent aggressor. Subsequently, the case of a line with two adjacent aggressors is discussed and it is shown how to generalize the technique for wide buses. In this work the efficiency of the detection mechanism is evaluated for both single and multiple faulty …
-
Time-based circuits for communication systems in advanced CMOS technology
… and an RF modulator based on ring oscillators in deep sub-micron CMOS processes. We introduce a VCO-based [sigma][delta] A/D converter utilizing a voltage-controlled ring oscillator (ring VCO) as a continuous-time integrator. We propose to replace conventional integrators designed with analog …
-
Application of three-dimensional circuit integration to global clock distribution
As the semi-conductor industry moves towards deep sub-micron designs, efficiency of chip-wide communication is becoming the limiting factor on system performance. One globally distributed signal with significant effect on system performance is the clock signal. In this paper utilization of …
-
Circuits and algorithms for pipelined ADCs in scaled CMOS technologies
… ADCs and general mixed signal design in deep sub-micron technologies.
-
Fabrication and characterization of nanostructured magnetic particles for applications in data storage
… systems for the study of magnetic phenomena at deep sub-micron length scales. We use interference lithography to pattern 200 nm-period arrays of nickel and cobalt nanomagnets. The nickel and cobalt are deposited via electroplating or evaporation/lift-off processes. Magnetometry techniques are …
-
Low energy digital circuit design using sub-threshold operation
Scaling of process technologies to deep sub-micron dimensions has made power management a significant concern for circuit designers. For emerging low power applications such as distributed micro-sensor networks or medical applications, low energy operation is the primary concern instead of speed, …
-
Characterization of optical interconnects
Interconnect has become a major issue in deep sub-micron technology. Even with copper and low-k dielectrics, parasitic effects of interconnects will eventually impede advances in integrated electronics. One technique that has the potential to provide a paradigm shift is optics. This project …
-
COPING WITH DISCREPANCIES OF THE MANUFACTURED WEIGHTS IN THRESHOLD LOGIC GATES
… an increasingly promising approach in the deep sub-micron design era. The gate that is implemented with threshold logic is called a Threshold Logic Gate (TLG). The logic output value of a Threshold Logic Gate (TLG) depends on the weighted sum of its inputs. Manufactured weights in the …
-
Energy-efficient analog-to-digital conversion for ultra-wideband radio
… improves the yield of the highly parallel ADC in deep sub-micron CMOS.
-
Study of subthreshold behavior of FinFet
The study of subthreshold behavior of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is critically important in the case of submicron devices for the successful design and implementation of digital circuits. Fin Field Effect Transistor (FinFET) is considered to be an alternate MOSFET …
-
Characterization and modeling of pattern dependencies in copper interconnects for integrated circuits
… as the leading interconnect technology for deep sub-micron features, where electroplating and chemical mechanical polish (CMP) processes have a vital role in the fabrication of integrated circuits. The processes both suffer from a similar problem: the copper electroplated profiles and the …
-
SCALABLE BUS ENCODING FOR ERROR-RESILIENT HIGH-SPEED ON-CHIP COMMUNICATION
Shrinking minimum feature size in deep sub-micron has made fabrication of progressively faster devices possible. The performance of interconnects has been a bottleneck in determining the overall performance of a chip. A reliable high-speed communication technique is necessary to improve the …
-
ANALYTICAL METHODS TO PROPAGATE AND DIAGNOSE SINGLE EVENT TRANSIENTS
… the probability of soft errors. In the current deep sub-micron technology, a small inaccuracy in computing the probability of occurrence of a soft error results in an unacceptably large chip failure rate. We propose a method that considers timing information to determine accurately the …
-
Active management of Cache resources
… processor design as the industry enters the deep sub-micron region of semiconductor design. The first set of challenges relates to the memory bottleneck. As the focus shifts from scaling processor frequency to scaling the number of cores, performance growth demands increasing die area. …
Page 1 of 2