Global ETD Search
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Showing 1 to 6 of 6 for “"VLSI Test"”.
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Symbolic techniques for VLSI test and diagnosis
Many problems in the domain of digital circuit testing and diagnosis demand the processing of a large number of circuit configurations. Recently, due to the development of binary decision diagrams (BDDs), symbolic methods have become a practical means of handling the large sets encountered in these …
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Design for Testability Techniques to Optimize VLSI Test Cost
High test data volume and long test application time are two major concerns for testing scan based circuits. The Illinois Scan (ILS) architecture has been shown to be effective in addressing both these issues. The ILS achieves a high degree of test data compression thereby reducing both the test …
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Static Learning for Problems in VLSI Test and Verification
… of electronic design automation (EDA) including: test-pattern-generation, logic and fault simulation, fault diagnosis, logic optimization, etc. While logic implications have assisted in solving several EDA problems, their usefulness has not been fully explored. We believe that logic implications …
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Dynamic scan chains : a novel architecture to lower the cost of VLSI test
… become larger and more complex, larger amount of test data is required to test them. This results in longer test application times, therefore, increasing cost of testing each chip. This thesis describes an architecture, named Dynamic Scan, that allows to reduce this cost by reducing the test data …
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Use of architectural-level primitives in system-level diagnosis and speed up of test vector generation
Test generation is an important part of a circuit as the test vectors are used during the design, manufacture, system integration, and throughout the life-cycle of the circuit in order to detect the presence of defects. The very large scale integration (VLSI) test generation problem has been one of …
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METHODS TO MINIMIZE LINEAR DEPENDENCIES IN TWO-DIMENSIONAL SCAN DESIGNS
… that uses multiple scan chains in parallel to test the Circuit Under Test (CUT). Linear Finite State Machines (LFSMs) are often used as on-board Pseudo Random Pattern Generators (PRPGs) in two-dimensional scan designs. However, linear dependencies present in the LFSM generated test-bit …