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Showing 1 to 4 of 4 for “"Test data compression"”.
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Scan test data compression using alternate Huffman coding
… is a good method for statistically compressing test data with high compression rates. Unfortunately, the on-‐chip decoder to decompress that encoded test data after it is loaded onto the chip may be too complex. With limited die area, the decoder complexity becomes a drawback. This makes …
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Digital core output test data compression architecture based on switching theory concepts: Model implementation and analysis
… support hardware for built-in self-testing (BIST) is of critical importance in the design and manufacture of VLSI circuits. This dissertation reports new space compression techniques for particular use in digital core based systems which facilitate designing compression networks …
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Novel methods for post-manufacturing and in-field testing of VLSI circuits/systems
… first we analyze and evaluate, the already known test data compression schemes for post-manufacturing testing and the DFT mechanisms for the enhancement of in-field testing and circuit reliability. We propose a new dictionary based test data compression method for post-manufacturing testing and we …
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Design for Testability Techniques to Optimize VLSI Test Cost
High test data volume and long test application time are two major concerns for testing scan based circuits. The Illinois Scan (ILS) architecture has been shown to be effective in addressing both these issues. The ILS achieves a high degree of test data compression thereby reducing both the test …