Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 55 for “"Technology scaling"”.
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Circuit designs for low-power and SEU-hardened systems
… devices is one of the primary motivations for technology scaling. Though advancements in device physics are moving at a very good pace, they might not be aggressive enough for now-a-day technology scaling trends. As a result, the MOS devices used for present day integrated circuits are pushed …
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Soft Error Modeling and Analysis for Microprocessors
… We apply our tool to investigate the impact of technology scaling on soft errors. We also propose an efficient online AVF estimation algorithm.
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A Comprehensive Study of Safe-Operating-Area, Biasing Constraints, and Breakdown in Advanced SiGe HBTs
… heterojunction bipolar transistor (HBT) BiCMOS technology. Technology scaling of SiGe HBTs for high frequency performance results on lower breakdown voltages, making operating voltage constraints an increasingly vital reliability consideration in SiGe HBTs from both a device and circuits …
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Application of three-dimensional circuit integration to global clock distribution
… integration to reduce the negative effects of technology scaling on clock signal distribution is investigated. A design is proposed that removes the clock distribution network from the same active plane as the logical functions of the system and places them on a separate, but electrically …
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Circuits and algorithms for pipelined ADCs in scaled CMOS technologies
CMOS technology scaling is creating significant issues for analog circuit design. For example, reduced signal swing and device gain make it increasingly difficult to realize high-speed, high-gain feedback loops traditionally used in switched capacitor circuits. This research involves two …
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Study of CMOS process variation by multiplexing analog characteristics
Aggressive technology scaling raises the need for efficient methods to characterize and model circuit variation at both the front and back end of line, where critical parameters such as threshold voltage and parasitic capacitance must be carefully modeled for accurate circuit performance. This …
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A time-interleaved Zero-Crossing-Based analog-to-digital converter
CMOS technology scaling has further reduced the output voltage swing and device gain, making it increasingly difficult to realize high-speed, high-gain op-amps with a stable feedback loop. The switched capacitor multiplier circuit in pipelined ADC is one application which has been hindered by …
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Analysis of variation in on-chip waveguide distribution schemes and optical receiver circuits
… distribution network can operate. The impact of technology scaling on the optical receiver circuit architecture is assessed with respect to variation. The robustness of the optical network is compared with that of an all-electrical signal distribution network.
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Design of fully digital inductors for low bandwidth filter applications
… manner makes it significantly more amenable for technology scaling. Fabricated in 65 nm CMOS process, the inductor operates from a 0.7 V supply voltage and consumes 528 μW. Measurement results show inductance values in the range of 150 μH to 1.5 mH can be achieved.
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ELECTRONIC DESIGN AUTOMATION TOOLS AND DESIGN STUDY FOR HETEROGENEOUS MONOLITHIC 3D INTEGRATED CIRCUITS
Technology scaling predicted by Moore's law is gradually slowing down and new alternatives to silicon-based transistors are being explored. Some of the most promising solutions make use of materials such as carbon nanotubes or ferroelectric layers in the gate stack. While such materials bring …
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Design and evaluation of a data-dependent low-power 8x8 DCT/IDCT
… Microelectronic Corporation 3-V 0.35 om CMOSP technology, this FDCT/IDCT design consumes 122.7/124.9 mW with clock frequency of 40MHz and processing rate of 320M sample/sec. With technology scaling to 0.35 om technology, the proposed design features lower switching capacitance per sample, i.e. …
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Input-Pattern-Independent Estimation of Peak Current, Peak Power Dissipation, and Maximum Voltage Variation in the Power Distribution Network of VLSI Circuits
Technology scaling improves the performance of circuits, but also increases the interactions between elements and increases the internal stresses in the circuit. For the design of reliable circuits, estimation of the worst-case attributes of the electrical/thermal interactions and the internal …
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CMOS Active Pixel Sensors for Digital Cameras: Current State-of-the-Art
… APS designs are challenging the old and mature technology of charged couple device (CCD) sensors. With the continuous improvements of APS architecture, pixel designs, along with the development of nanometer CMOS fabrications technologies, APS are optimized for optical sensing. In addition, APS …
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Managing Many-Core Aging
Many-core scaling now faces a power wall. The gap between the number of cores that fit on a die and the number that can operate simultaneously under the power budget is rapidly increasing with technology scaling. In future designs, the majority of the cores will necessarily have to be dormant at …
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Ordered Mesh Network Interconnect (OMNI) : design and implementation of in-network coherence
CMOS technology scaling has enabled increasing transistor density on chip. At the same time, multi-core processors that provide increased performance, vis-a'-vis power efficiency, have become prevalent in a power constrained environment. The shared memory model is a predominant paradigm in such …
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Field solver technologies for variation-aware interconnect parasitic extraction
… high density onchip integration by constantly scaling down the device and interconnect feature size. As a consequence of the ongoing technology scaling (from 45nm to 32nm, 22nm and beyond), geometrical variabilities induced by the uncertainties in the manufacturing processes are becoming more …
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Microarchitectural Level Power Analysis And Optimization In Single Chip Parallel Computers
… with improving technologies need to be explored. Technology scaling increases the effects of wire latencies, inductive effects, noise and crosstalk in on-chip communication, limiting the performance of DSM designs. Power efficient performance gains from Instruction Level Parallelism (ILP) are …
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Self-Scaling Evolution of Analog Computation Circuits
… of tomorrow*s electronic devices at current technology scaling limits. However, analog computation is plagued by the difficulty of designing complex computational circuits, programmability, as well as the inherent lack of accuracy and precision when compared to digital implementations. In …
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Single event upset hardened CMOS combinational logic and clock buffer design
… free with the help of error correction codes. Technology scaling is driving up the SEU rate of combinational logic and it is predicted that the soft error rate (SER) of combinational logic may dominate the SER of unpro-tected memory by the year 2011. Hence a robust combinational logic …
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Power-efficient high-speed interface circuit techniques
… have become the new challenge to enable the scaling of computing systems, ranging from mobile devices to high-end servers. Demand for aggregate I/O bandwidth has been driven by applications including high-speed ethernet, backplane micro-servers, memory, graphics, chip-to-chip and network …
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