Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 30 for “"Shared-Memory Multiprocessors"”.
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Parallel architectural simulations on shared memory multiprocessors
… excessive amounts of processing power and memory. One way to meet these requirements of detailed computer simulations is to execute them on multiprocessors.
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The raven kernel: a microkernel for shared memory multiprocessors
… is a small, lightweight operating system for shared memory multiprocessors. Raven is characterized by its movement of several traditional kernel abstractions into user space. The kernel itself implements tasks, virtual memory management, and low level excep-tion dispatching. All thread …
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Cooperative Data Transfer: Fast Message -Passing on Shared-Memory Multiprocessors
This work describes and tests eight point-to-point send operations that are implemented using Cooperative Data Transfer. Several global communication operations are also presented that reduce synchronization costs even for small messages. Cooperative Data Transfer performs well on many parallel …
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Architectural Support for Scalable Speculative Parallelization in Shared -Memory Multiprocessors
In this thesis, we also propose a new approach to reduce the cost of handling cross-thread data dependence violations: run-time learning. Using a new module called the Violation Prediction Table, the hardware learns to stall a thread when it seems likely to trigger a squash, and to release it when …
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Reducing memory access delays in large-scale shared-memory multiprocessors
Memory access time is a key factor limiting the performance of large-scale, shared-memory multiprocessors. In such systems, limited bandwidth in the interconnection between the processors and the memories, coupled with long delays resulting from network and memory conflicts, can produce serious …
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Adaptive and integrated data cache prefetching for shared memory multiprocessors
Memory latency has always been a major issue in shared-memory multiprocessors and high-speed systems. This is even more true as the gap between processor and memory speeds continues to grow. Data prefetching has been proposed as a means of addressing the data access penalty problem. Data …
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PARASPICE: A parallel direct circuit simulator for shared-memory multiprocessors
… Therefore, it is suitable for a wide range of shared-memory multiprocessors. The implementation of the approach in SPICE2 resulted in a portable parallel direct circuit simulator, PARASPICE. The superior performance of PARASPICE is demonstrated on an eight-CE Alliant FX/80 using a number of …
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Hardware for Speculative Run-Time Parallelization in Distributed Shared -Memory Multiprocessors
The simulation results show that for the applications with dependence, the NPA and PA provide the best performance, because they are less complicated than the SUPAR algorithm, but still can recover efficiently from dependence violation. For applications without dependence, the performances of all …
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Architectural Alternatives to Reduce Remote Conflict Misses in Shared-Memory Multiprocessors
… further with the ability of migrating data using memory lines that are not actively used. The resulting architecture is termed as EX-NUMA. The extra design overhead of EX-NUMA over NUMA-RC is minimal and is shown to be effective: our simulation results suggest that EX-NUMA outperforms both NUMA-RC …
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On the implementation and effectiveness of autoscheduling for shared-memory multiprocessors
… model of computation on conventional shared-memory multiprocessors. In autoscheduling, the partitioning and scheduling of computations for parallel execution are performed by means of drive code injected by the compiler at the entry and exit points of each schedulable unit (tasks).
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Processor parallelism considerations and memory latency reduction in shared memory multiprocessors
… in instruction scheduling constraints, memory latencies, and synchronization overhead, making it difficult to determine which architecture can achieve the best performance on a given program. Trace-driven simulations and analytic models are used to compare the instruction-level …
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Architectural and Compiler Support to Hide Coherence Misses in Distributed Shared-Memory Multiprocessors
… improvements of about 30%, regardless of the memory size. For the applications studied, while for the the average improvement of data forwarding is smaller than in data forwarding, neither technique outperforms the other in all cases. The proposed integrated techniques are able to further …
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Memory latency reduction via data prefetching and data forwarding in shared memory multiprocessors
… mechanism, data forwarding, for reducing memory latency due to interprocessor communication in cache coherent, shared memory multiprocessors. The benefits of prefetching and forwarding are considered for large, numerical application codes with loop-level and vector parallelism. Data …
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Hardware and compiler support for cache coherence in large-scale shared-memory multiprocessors
Restriction data tranferred 2014-07-01T11:21:19-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission
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Fine-grain producer-initiated communication in cache-coherent multiprocessors
Shared-memory multiprocessors are becoming increasingly popular as a high-performance, easy to program, and relatively inexpensive choice for parallel computation. However, the performance of shared-memory multiprocessors is limited by memory latency. Memory latencies are higher in multiprocessors …
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Communication and Synchronization in Parallel Computation
… overheads in parallel algorithms executing on shared memory multiprocessors.
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Memory management and rollback recovery in parallel architectures
This thesis examines memory management and rollback recovery in parallel architectures. Three memory management strategies for rapid rollback recovery are studied in this thesis. The first is a cache-based error recovery scheme for shared memory multiprocessors. The second is a design for …
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Architectural and Software Support for Executing Numerical Applications on High Performance Computers
… large amounts of computing power. Although shared memory multiprocessors provide a cost-effective platform for parallel execution of numerical programs, parallel processing has not delivered the expected performance on these machines. There are two crucial steps in parallel execution of …
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A class library approach to concurrent object-oriented programming with applications to VLSI CAD
… The interface supports uniprocessors, shared memory multiprocessors, distributed memory multicomputers, and hybrid architectures comprising network-connected clusters of uni- and multiprocessors. The library currently supports workstations from Sun, shared memory multiprocessors from …
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Parallel algorithms for CAD with applications to circuit extraction
… for VLSI circuit extraction on hypercube and shared memory multiprocessors. We give the performance results of the algorithms on an Intel iPSC2 hypercube and an Encore Multimax shared memory multiprocessor, for different partitioning strategies.
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