Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 11 of 11 for “"Logic Level"”.
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Simulation of faults causing analog behavior in digital circuits
… faults that are difficult to model using a logic-level or switch-level simulator, and the simulation of transient faults that have a time-varying characteristic during the simulation. The simulation of these types of faults is inherently expensive because it requires detailed circuit-level …
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Design of Area-Efficient Integrated Gate Drivers
… such systems, but with limited drive current and logic level voltage signals, it is unable to directly turn on a discrete power MOSFET. Gate drivers serve as the critical interface between the controller output and the power MOSFET. This thesis explores some of the considerations in designing a …
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A system for microarchitecture and logic optimization
… the design of numerous behavioral synthesis and logic synthesis tools. This thesis spans two levels of the design process by examining optimization at both the register-transfer level and at the logic level. More specifically, this thesis addresses the following two problems: (1) performing logic …
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Design Verification for Sequential Systems at Various Abstraction Levels
… different core algorithms at various abstraction levels. At the logic level, we focus on incorporating a set of novel ideas to existing formal verification approaches. First, we present a number of powerful optimizations to improve the performance and capacity of a typical SAT-based bounded model …
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Binäre Expression-Diagramme
Durch die stetig steigenden Anforderungen an die Leistungsfähigkeit moderner Schaltungen besteht fortwährend die Notwendigkeit, immer effizientere Datenstrukturen und darauf operierende Algorithmen zur Beherrschung der steigenden Komplexitäten zu entwicklen. Die vorliegende Arbeit stellt Theorie …
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Gate-level Leakage Assessment and Mitigation
… This thesis presents a methodology called Gate-level Leakage Assessment (GLA), which evaluates the power-based side-channel leakage of an integrated circuit at design time. By combining side-channel leakage assessment with power simulations on the gate-level netlist, GLA is able to pinpoint the …
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Single event upset hardened CMOS combinational logic and clock buffer design
… charge collection, which may manifest as a wrong logic level causing failure. Soft errors or Single Event Upsets (SEU) caused by radiation strikes are one of the main failure modes in a VLSI circuit. Previous work predicts that soft error rate may dominate the failure rate in VLSI circuit compared …
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Fault Simulation and Transistor-Level Test Generation for Physical Failures in Mos Circuits
… were traditionally developed at the gate-level based on the stuck-at fault model. However, with the advent of VLSI MOS technology, this fault model is not applicable. In order to reduce the number of faults which need to be considered in the system so that the effort for test generation …
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On a Viterbi decoder design for low power dissipation
… is reduction of dynamic power dissipation at logic level in the standard cell design environment. We considered two methods, clock-gating and toggle-filtering, in our design. A Viterbi decoder consists of five blocks. The clock-gating was applied to the survivor path storage block and the …
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Techniques for VLSI Circuit Optimization Considering Process Variations
… problem. The BIDS problem is solved at the logic level, with look-up table based approximation of net lengths for early variation awareness.In the context of dynamic variation compensation, a delay detection circuit is used to identify the uncertainty in critical path delay. The delay …
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Digital communication receiver algorithms and architectures for reduced complexity and high throughput
… with less than 1 dB SNR loss, according to logic-level simulations performed for an example 25-tap frequency-selective filter.