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Showing 1 to 13 of 13 for “"CMOS scaling"”.

  1. A sampling jitter tolerant continuous-time pipeline ADC

    … in the bandwidth and sampling speed due to CMOS scaling have brought the deleterious effects of sampling clock jitter to the forefront. Any jitter in the sampling clock edge adds a random error to the input signal thereby limiting the maximum achievable signal-to-noise ratio (SNR), and hence …

    mit Repository record for A sampling jitter tolerant continuous-time pipeline ADC (opens in a new tab)

  2. A time-interleaved Zero-Crossing-Based analog-to-digital converter

    CMOS technology scaling has further reduced the output voltage swing and device gain, making it increasingly difficult to realize high-speed, high-gain op-amps with a stable feedback loop. The switched capacitor multiplier circuit in pipelined ADC is one application which has been hindered by …

    mit Repository record for A time-interleaved Zero-Crossing-Based analog-to-digital converter (opens in a new tab)

  3. Monolithic RF frontends for ubiquitous wireless connectivity

    … and achievable frequency range benefit from CMOS scaling.

    mit Repository record for Monolithic RF frontends for ubiquitous wireless connectivity (opens in a new tab)

  4. Engineered substrates for coplanar integration of lattice-mismatched semiconductors with silicon

    As we approach the end of traditional CMOS scaling, further improvements in integrated circuit performance and functionality will become limited by the inherently low carrier mobility and indirect bandgap of silicon. These performance shortcomings can be supplemented with high performance …

    mit Repository record for Engineered substrates for coplanar integration of lattice-mismatched semiconductors with silicon (opens in a new tab)

  5. Nano-scale metal contacts for future III-V CMOS

    … continue to scale down in size, conventional Si CMOS is reaching its physical limits and alternative technologies are needed to extend Moore's law. Among different candidates, MOSFETs with a III-V compound semiconductor channel are of great interest. Specifically, designs with an InGaAs channel …

    mit Repository record for Nano-scale metal contacts for future III-V CMOS (opens in a new tab)

  6. Digitally-Assisted RF IC Design Techniques for Reliable Performance

    … industries have competitively scaled down CMOS devices to attain benefits of low cost, high performance, and high integration density in digital integrated circuits. On the other hand, deep scaled technologies inextricably accompany a large process variation, supply voltage scaling, and …

    purdue-thes Repository record for Digitally-Assisted RF IC Design Techniques for Reliable Performance (opens in a new tab)

  7. Drifting-dipole noise model of nanometer MOSFETs for radio frequency integrated circuit design

    Recent advances in nanometer CMOS scaling technology have made transistors capable of operating at hundreds of gigahertz, and opened a new era of high performance, low cost system-on-chip (SOC) designs for multi-gigabit-per-second wireless communication. However, such achievements also bring new …

    uiuc Repository record for Drifting-dipole noise model of nanometer MOSFETs for radio frequency integrated circuit design (opens in a new tab)

  8. InGaAs self-aligned HEMT for logic applications

    As CMOS scaling approaches the end of the roadmap it has become a matter of great urgency to explore alternative options to conventional Si devices for logic applications. The high electron mobilities of III-V based compounds makes them an attractive option for use as a channel material. Of these …

    mit Repository record for InGaAs self-aligned HEMT for logic applications (opens in a new tab)

  9. Energy-efficient smart embedded memory design for IoT and AI

    … (SoC) applications, thanks to aggressive CMOS scaling, which keeps on providing higher storage density per unit silicon area. As memory sizes continue to grow, increased bit-cell variation limits the supply voltage (Vdd) scaling of the memory. Furthermore, larger memories lead to data …

    mit Repository record for Energy-efficient smart embedded memory design for IoT and AI (opens in a new tab)

  10. Energy-efficient SRAM design in 28nm FDSOI Technology

    As CMOS scaling continues to sub-32nm regime, the effects of device variations become more prominent. This is very critical in SRAMs, which use very small transistor dimensions to achieve high memory density. The conventional 6T SRAM bit-cell, which provides the smallest cell-area, fails to operate …

    mit Repository record for Energy-efficient SRAM design in 28nm FDSOI Technology (opens in a new tab)

  11. Reconfigurable Discrete-time Analog FIR filters for Wideband Analog Signal Processing

    … provides robustness in the presence of digital CMOS scaling. The primary work presented in this dissertation is the design of wideband analog finite impulse response (AFIR) filters. Analog FIR filters have been used as low pass filters for out-of-band rejection in narrow-band applications. …

    vt Repository record for Reconfigurable Discrete-time Analog FIR filters for Wideband Analog Signal Processing (opens in a new tab)

  12. Characterization and Modeling of Low Frequency Noise and Dielectric Traps in Scaled MOSFET Devices

    CMOS scaling has pushed the industry toward circuits and systems of better performance, higher density, and lower cost for electronic products through the past several decades. The high-K materials are introduced into the MOSFET structure to reduce the gate leakage current, increase the gate …

    ohiolink Repository record for Characterization and Modeling of Low Frequency Noise and Dielectric Traps in Scaled MOSFET Devices (opens in a new tab)