Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 28 for “"3D IC"”.
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Analog-digital co-existence in 3D-IC
Ubiquitous mobile communication creates an increasing demand for high data rates, complex modulation schemes and low power design. The cost and performance benefits of conventional lithographic scaling are diminishing as process cost increases exponentially. 3D integration has the potential to keep …
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Placement for fast and reliable through-silicon-via (TSV) based 3D-IC layouts
… found in three-dimensional integrated circuits (3D ICs) that use through-silicon vias (TSVs) at placement stage. Four main works that support this goal are included. In the first work, wirelength of TSV-based 3D ICs is the main focus. In the second work, stress-induced carrier mobility variation …
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Design Automation and Evaluation Of Emerging 3D – IC Technology Using Stacked Horizontal Nanowires
Miniaturization of integrated circuits (ICs) has continuously enabled advancement in modern technology. This miniaturization trend, also known as Moore’s law, needs to be maintained intact to meet the current day computational demands. Further miniaturization of transistors below sub 10nm regime …
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PI AND EMI ANALYSIS OF 3D IC SYSTEM WITH TSVS AND CO-PACKAGED OPTICS
… high-capacity, high-density, high-power optical links for data center communications, co-packaged optics is a promising solution. When the three-dimensional (3D) IC and optic engines are integrated into the same package, the design of such systems in terms of signal integrity, power …
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Numerical analysis of TSV/micro-bump deformation due to chip misalignment and thermal processing in 3D IC packages
Three-dimensional (3D) stacking of integrated circuits (ICs) is an enabling technology in the advancement of the microelectronics industry. 3D stacking enables increased device density per volume and improved electrical performance through short vertical interconnect paths. Mechanical reliability …
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Stability analysis for SRAM cells with TSV induced stress in 3D ICs
Three-dimensional integrated circuits (3D-IC) have emerged as promising candidates to overcome the interconnect bottlenecks of nanometer scale designs while also helping to reduce wire delay and increase memory throughput. While this technology offers many potential advantages, it also produces …
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Asynchronous 3D (Async3D): Design Methodology and Analysis of 3D Asynchronous Circuits
<p>This dissertation focuses on the application of 3D integrated circuit (IC) technology on asynchronous logic paradigms, mainly NULL Convention Logic (NCL) and Multi-Threshold NCL (MTNCL). It presents the Async3D tool flow and library for NCL and MTNCL 3D ICs. It also analyzes NCL and MTNCL …
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Characterization and requirements for Cu-Cu bonds for three-dimensional integrated circuits
Three-dimensional integrated circuit (3D IC) technology enables heterogeneous integration of devices fabricated from different technologies, and reduces global RC delay by increasing the device density per unit chip area. Wafer-level Cu-Cu thermocompression bonding provides an attractive route to …
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ELECTRONIC DESIGN AUTOMATION TOOLS AND DESIGN STUDY FOR HETEROGENEOUS MONOLITHIC 3D INTEGRATED CIRCUITS
Technology scaling predicted by Moore's law is gradually slowing down and new alternatives to silicon-based transistors are being explored. Some of the most promising solutions make use of materials such as carbon nanotubes or ferroelectric layers in the gate stack. While such materials bring …
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Electro-Thermal Codesign in Liquid Cooled 3D ICs: Pushing the Power-Performance Limits
… coming years will continue to witness a significant increase in CPU power dissipation due to advanced multi-core architectures and 3D integration technologies. Nowadays the problems of increased chip power density, leakage power and system temperatures have become major obstacles for further …
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Graphene Nanotechnology the Next Generation Logic, Memory and 3D Integrated Circuits
Floating gate transistor is the basic building block of non-volatile flash memory, which is one of the most widely used memory gadgets in modern micro and nano electronic applications. Recently there has been a surge of interest to introduce a new generation of memory devices using graphene …
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Thermo-mechanical stress measurement and analysis in three dimensional interconnect structures
… to overcome the wiring limit imposed on device density and performance with continued scaling. The application of TSV (Through-Silicon Via) is essential for 3D IC integration. TSVs are embedded into the silicon substrate to form vertical, electrical connections between stacked IC chips. …
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Effects of underfill material on solder deformation and damage in 3D packages
… the effects of the introduction of a periodic boundary condition and the presence of underfill material on the stress and strain fields and evolution of failure of an FEA model that is representative of a solder joint in a 3D IC package. The model solder joint is placed between two silicon …
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Environmentally benign manufacturing of three dimensional integrated circuits
… novel materials have been introduced into the semiconductor industry to enable continued improvements in performance and cost as predicted by Moore's law. It has become important now more than ever to include an environmental impact evaluation of future technologies, before they are introduced …
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Towards low-power yet high-performance networks-on-chip
A network-on-chip (NoC), the de-facto communication backbone in manycore processors, consumes a significant portion of total chip power, competing against the computation cores for the limited power and thermal budget. On the other hand, overall system performance of manycore chips increasingly …
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DENSE 3D HETEROGENEOUS INTEGRATION USING SELECTIVE COBALT ALD DEPOSITION AND RECONSTITUTED TIERS
… bonding, a Cu/Gap/Cu three-layered structure, which emulates 3D ICs stacking, is fabricated and carefully characterized. The testbed shows seamless Co interconnection between the Cu pads after Co ALD deposition for 1000 cycles. The electrical measurements demonstrate over 90% yield, which prove …
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ERNI-3D : a technology-generic tool for interconnect reliability projections in 3D integrated circuits
Recent developments in semiconductor processing technology has enabled the fabrication of a single integrated circuit (IC) with multiple device-interconnect layers or wafers stacked on each other. This approach is commonly referred to as the 3D integration of ICs. Although there has been …
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3D modeling and integration of current and future interconnect technologies
… performance estimation before circuit fabrication which reduces the computational resource requirement as well as the time constraints. We propose a new capacitance models for interconnect lines in multilevel interconnect structures by geometrically modeling the electrical flux lines of the …
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Enhanced Heat Transfer Performance by Shape Optimization of a Non-axisymmetric Droplet Evaporating on a Heated Micropillar
… by Shape Optimization of a Non-axisymmetric Droplet Evaporating on a Heated Micropillar</p> <p>By</p> <p>Haotian Wu</p> <p>Department of Mechanical Engineering and Materials Science</p> <p>Washington University in St. Louis, 2019</p> <p>Research Advisor: Professor Damena Agonafer</p> …
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