Abstract Partitioning and Routing of Logic Networks for Custom Module Generation

This thesis describes a module planner for decomposing arbitrary functional specifications of any complexity into abstract cells for custom-VLSI module generation. A graph representing random logic is partitioned and the nodes are packed into abstract cell output descriptions. A type of terminal propagation called gain-biasing has been implemented, and is used during the partitioning process to account for the clustering of logic gates with respect to external I/O port positions. Interconnecting the cells of a module is done with through-the-cell routing. A relative pin assignment algorithm has been developed for ordering terminals along the internal abstract cell boundaries. In routing signals between nonadjacent cells, a global wiring penalty function is employed that not only considers previous routes, but also considers gate complexity within the cells of a module. Finally, an efficient optimization algorithm is used for minimizing the number of routing tracks running through the module. The abstract cell files which are generated by the planner consist of gate and pass transistor textual functions along with port positions. This textual data is in a technology independent format which can then be given to a cell synthesizer to generate technology-specific, but process-independent geometric layouts.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Computer Science

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2014

Author dc:creator

• Healey, Steven Thomas

• Computer Science

Identifier

(UMI)AAI8721654

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/69575