Abstract Partitioning and Routing of Logic Networks for Custom Module Generation
type: CreativeWork
description: This thesis describes a module planner for decomposing arbitrary functional specifications of any complexity into abstract cells for custom-VLSI module generation. A graph representing random logic is partitioned and the nodes are packed into abstract cell output descriptions. A type of terminal propagation called gain-biasing has been implemented, and is used during the partitioning process to account for the clustering of logic gates with respect to external I/O port positions. Interconnecting the cells of a module is done with through-the-cell routing. A relative pin assignment algorithm has been developed for ordering terminals along the internal abstract cell boundaries. In routing signals between nonadjacent cells, a global wiring penalty function is employed that not only considers previous routes, but also considers gate complexity within the cells of a module. Finally, an efficient optimization algorithm is used for minimizing the number of routing tracks running through the module. The abstract cell files which are generated by the planner consist of gate and pass transistor textual functions along with port positions. This textual data is in a technology independent format which can then be given to a cell synthesizer to generate technology-specific, but process-independent geometric layouts.
abstract: This thesis describes a module planner for decomposing arbitrary functional specifications of any complexity into abstract cells for custom-VLSI module generation. A graph representing random logic is partitioned and the nodes are packed into abstract cell output descriptions. A type of terminal propagation called gain-biasing has been implemented, and is used during the partitioning process to account for the clustering of logic gates with respect to external I/O port positions. Interconnecting the cells of a module is done with through-the-cell routing. A relative pin assignment algorithm has been developed for ordering terminals along the internal abstract cell boundaries. In routing signals between nonadjacent cells, a global wiring penalty function is employed that not only considers previous routes, but also considers gate complexity within the cells of a module. Finally, an efficient optimization algorithm is used for minimizing the number of routing tracks running through the module. The abstract cell files which are generated by the planner consist of gate and pass transistor textual functions along with port positions. This textual data is in a technology independent format which can then be given to a cell synthesizer to generate technology-specific, but process-independent geometric layouts.
author: Healey, Steven Thomas
keywords: Computer Science
date published: 2014-12-15T19:25:54Z
date modified: 2026-07-22T22:26:01Z
provider: University of Illinois - Urbana-Champaign
publisher: Networked Digital Library of Theses and Dissertations
type: WebPage
source organization: University of Illinois at Urbana-Champaign

PropertyValue
property ID: Handle
value: http://hdl.handle.net/2142/69575