Minimal Parallel Binary Adders With And/or Gates and a Scheme for a Compact Parallel Multiplier

As we enter the era of VLSI, the compactness of logic networks becomes more and more important. A more compact logic network leads to an IC chip of smaller size, lower power consumption, higher speed, and higher yield. We usually design logic networks with a minimum number of gates and a minimum number of connections. This design approach tends to reduce the chip area covered by the network and appears satisfactory if we first use the minimum logic network as a model and then make modifications according to constraints necessary to implement later design stages.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Computer Science

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2014

Author dc:creator

• Cheng, Bin

• Computer Science

Identifier

(UMI)AAI8302829

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/69510