Minimal Parallel Binary Adders With And/or Gates and a Scheme for a Compact Parallel Multiplier
As we enter the era of VLSI, the compactness of logic networks becomes more and more important. A more compact logic network leads to an IC chip of smaller size, lower power consumption, higher speed, and higher yield. We usually design logic networks with a minimum number of gates and a minimum number of connections. This design approach tends to reduce the chip area covered by the network and appears satisfactory if we first use the minimum logic network as a model and then make modifications according to constraints necessary to implement later design stages.
University of Illinois - Urbana-Champaign
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University of Illinois at Urbana-Champaign