Minimal Parallel Binary Adders With And/or Gates and a Scheme for a Compact Parallel Multiplier
type: CreativeWork
description: As we enter the era of VLSI, the compactness of logic networks becomes more and more important. A more compact logic network leads to an IC chip of smaller size, lower power consumption, higher speed, and higher yield. We usually design logic networks with a minimum number of gates and a minimum number of connections. This design approach tends to reduce the chip area covered by the network and appears satisfactory if we first use the minimum logic network as a model and then make modifications according to constraints necessary to implement later design stages.
abstract: As we enter the era of VLSI, the compactness of logic networks becomes more and more important. A more compact logic network leads to an IC chip of smaller size, lower power consumption, higher speed, and higher yield. We usually design logic networks with a minimum number of gates and a minimum number of connections. This design approach tends to reduce the chip area covered by the network and appears satisfactory if we first use the minimum logic network as a model and then make modifications according to constraints necessary to implement later design stages.
author: Cheng, Bin
keywords: Computer Science
date published: 2014-12-15T19:25:18Z
date modified: 2026-07-22T22:26:01Z
provider: University of Illinois - Urbana-Champaign
publisher: Networked Digital Library of Theses and Dissertations
type: WebPage
source organization: University of Illinois at Urbana-Champaign

PropertyValue
property ID: Handle
value: http://hdl.handle.net/2142/69510