iSITE: Automatic circuit synthesis for double-metal CMOS VLSI circuits

Very large scale integrated (VLSI) circuit technology allows one to manufacture chips with several million devices. Designing such large circuits cannot be accomplished without design automation tools and computer-aided design tools. This thesis addresses the problem of automatic circuit synthesis for double-metal CMOS technology. Large circuits are partitioned into cells and represented as incidence matrices. The rows and columns of these matrices are folded to minimize the area. A symbolic layout is then generated for each matrix. This symbolic layout is then used to generate the physical mask layers necessary for fabrication in the metal-metal matrix methodology.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Gee, Perry

Contributors dc:contributor

• Hajj, Ibrahim N.

• Engineering, Electronics and Electrical

Statement dc:rights

• Copyright 1989 Gee, Perry

Language dc:language

eng

Identifier

AAI9010861
(UMI)AAI9010861

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/19216