iSITE: Automatic circuit synthesis for double-metal CMOS VLSI circuits
Very large scale integrated (VLSI) circuit technology allows one to manufacture chips with several million devices. Designing such large circuits cannot be accomplished without design automation tools and computer-aided design tools. This thesis addresses the problem of automatic circuit synthesis for double-metal CMOS technology. Large circuits are partitioned into cells and represented as incidence matrices. The rows and columns of these matrices are folded to minimize the area. A symbolic layout is then generated for each matrix. This symbolic layout is then used to generate the physical mask layers necessary for fabrication in the metal-metal matrix methodology.
University of Illinois - Urbana-Champaign
Networked Digital Library of Theses and Dissertations
University of Illinois at Urbana-Champaign