TOWARDS INTEGRATION OF GRAPHENE IN ADVANCED CMOS INTERCONNECT TECHNOLOGY

The integration of graphene into existing state-of-the-art semiconductor manufacturing is a topic of worldwide interest. With its unprecedented electrical, thermal and mechanical properties, graphene is ideally suited for back-end of line (BEOL) technology to boost the performance of on-chip copper (Cu) interconnects. However, the lack of BEOL compatible methods has stymied the true evaluation of Cu/graphene hybrid (Cu-G) technology. The objectives of this thesis proposal are to demonstrate BEOL-compatible graphene growth techniques, and explore various avenues for practical integration of graphene in order to achieve better electrical, thermal and reliability metrics than traditional interconnect technology.

Name thesis:degree_name

Doctor of Philosophy (PhD)

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical and Computer Engineering

Year

2016

Author dc:creator

• Mehta, Ruchit

Contributors dc:contributor

• Zhihong Chen
• David B Janes
• Amy M Marconnet
• Xiulin Ruan

• diffusion barrier
• graphene
• graphene-copper hybrid
• PECVD
• thermal management

Repository record dc:identifier

https://docs.lib.purdue.edu/open_access_dissertations/1392

OAI identifier oai:identifier

oai:docs.lib.purdue.edu:open_access_dissertations-2608