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Design and evaluation of an adaptable vector coprocessor for multicores

Abstract

dc:description.abstract

Future applications for multi-core processor systems will require increased signal processing power along with increased resource utilization and decreased power consumption. Conservative power consumption will be of paramount importance primarily for battery-powered portable multi-core platforms (e.g., advanced cell phones, tablet computers, etc.). This thesis investigates the robustness, efficiency and effectiveness of vector coprocessor sharing policies in multi-core environments. Vector coprocessor sharing is based on an innovative design for a vector lane that forms the building block for the creation of larger vector coprocessors. This innovative lane design contains a floating-point multiply unit, a floating-point add/subtract unit, a miscellaneous function unit, a load/store unit, and a vector register file. The design was prototyped and benchmarked on a field programmable gate array (FPGA) for a multitude of configurations to evaluate the performance and power consumption. The configurations included one or two host processors and two, four, eight, sixteen or thirty-two lanes. Sample applications in benchmarking were the fast Fourier transform, finite impulse response filter, matrix multiplication and LU matrix decomposition. As an additional experiment, a reconfigurable unit was added to the lane and configured as either a combined floating-point multiply/add or a floating-point divide to better match the needs of specific applications. The results show the versatility of the design towards high performance and controllable power consumption.

Degree

thesis:*
Name thesis:degree_name
Master of Science in Electrical Engineering - (M.S.)
Discipline thesis:degree_discipline
Electrical and Computer Engineering
Year
2011

Author and committee

dc:creator, dc:contributor.*
Author dc:creator
  • Steele, Timothy William
Contributors dc:contributor
  • Sotirios Ziavras
  • Edwin Hou
  • Jie Hu

Subjects

dc:subject × 3

Identifiers

dc:identifier.*
Repository record dc:identifier
https://digitalcommons.njit.edu/theses/102
OAI identifier oai:identifier
oai:digitalcommons.njit.edu:theses-1101

Chain of custody

source
Harvested from
NJIT
Base URL
digitalcommons.njit.edu/do/oai/
Last updated
2026-07-24
Source record
OAI-PMH GetRecord
citation

Steele, Timothy William. Design and evaluation of an adaptable vector coprocessor for multicores. 2011. https://digitalcommons.njit.edu/theses/102