{"id":{"repo_id":"wvu","oai_identifier":"oai:researchrepository.wvu.edu:etd-2177"},"canonical_url":"https://search.dev.ndltd.org/etd/wvu/oai:researchrepository.wvu.edu:etd-2177","repository":{"repo_id":"wvu","name":"West Virginia University","base_url":"https://researchrepository.wvu.edu/do/oai/"},"display":{"title":"CMOS fingerprint sensor electrostatic modeling","abstract":"The use of Biometrics in personal identification is an important emerging technology in modern electronic society. Fingerprints are one of the most popular biometric technologies, currently used in majority of biometric applications. In recent years, solid-state capacitive fingerprint sensors which image fingerprints using Silicon CMOS Technology are gaining much acceptance in the market. This research work is carried out to quantify and explore approaches for achieving improved sensitivity of the capacitive imaging process through reduction of parasitic capacitances and sensor cell scaling for future generation devices. Evaluation of sensor cell and array geometries was completed using a commercial 2-D electrostatic field solver. The modeling activities performed include analysis of sensor cell and sensor plate size, their relationships, evaluation of ESD ring coupling, and exploration of cell and array layout approaches for achieving reduced parasitic capacitance.","abstract_html":"The use of Biometrics in personal identification is an important emerging technology in modern electronic society. Fingerprints are one of the most popular biometric technologies, currently used in majority of biometric applications. In recent years, solid-state capacitive fingerprint sensors which image fingerprints using Silicon CMOS Technology are gaining much acceptance in the market. This research work is carried out to quantify and explore approaches for achieving improved sensitivity of the capacitive imaging process through reduction of parasitic capacitances and sensor cell scaling for future generation devices. Evaluation of sensor cell and array geometries was completed using a commercial 2-D electrostatic field solver. The modeling activities performed include analysis of sensor cell and sensor plate size, their relationships, evaluation of ESD ring coupling, and exploration of cell and array layout approaches for achieving reduced parasitic capacitance.","abstract_has_math":false,"creators":["Soora, Praveen Kumar"],"institution":null,"degree_name":"MS","degree_level":"Thesis","degree_discipline":"Lane Department of Computer Science and Electrical Engineering","degree_department":null,"school":null,"contributors":["Lawrence A. Hornak."],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2001,"date_issued":"2001-05-01T07:00:00Z","date_published":"2001-05-01T07:00:00Z","updated_at":"2026-07-24T06:15:23Z","subjects":["Electrical engineering","Biomedical engineering"],"languages":[],"rights":[],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["https://researchrepository.wvu.edu/etd/1174"],"render_values":[{"text":"https://researchrepository.wvu.edu/etd/1174","href":"https://researchrepository.wvu.edu/etd/1174","code":true}]}]},"links":{"outbound_url":"https://doi.org/10.33915/etd.1174","outbound_label":"DOI","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Lawrence A. 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Fingerprints are one of the most popular biometric technologies, currently used in majority of biometric applications. In recent years, solid-state capacitive fingerprint sensors which image fingerprints using Silicon CMOS Technology are gaining much acceptance in the market. This research work is carried out to quantify and explore approaches for achieving improved sensitivity of the capacitive imaging process through reduction of parasitic capacitances and sensor cell scaling for future generation devices. Evaluation of sensor cell and array geometries was completed using a commercial 2-D electrostatic field solver. The modeling activities performed include analysis of sensor cell and sensor plate size, their relationships, evaluation of ESD ring coupling, and exploration of cell and array layout approaches for achieving reduced parasitic capacitance."]},{"key":"dc:title","label":"Title","values":["CMOS fingerprint sensor electrostatic modeling"]}]}],"canonical_facts":{"dc:contributor":["Lawrence A. Hornak."],"dc:creator":["Soora, Praveen Kumar"],"dc:date.available":["2019-01-17T08:00:00Z"],"dc:description.abstract":["The use of Biometrics in personal identification is an important emerging technology in modern electronic society. Fingerprints are one of the most popular biometric technologies, currently used in majority of biometric applications. In recent years, solid-state capacitive fingerprint sensors which image fingerprints using Silicon CMOS Technology are gaining much acceptance in the market. This research work is carried out to quantify and explore approaches for achieving improved sensitivity of the capacitive imaging process through reduction of parasitic capacitances and sensor cell scaling for future generation devices. Evaluation of sensor cell and array geometries was completed using a commercial 2-D electrostatic field solver. The modeling activities performed include analysis of sensor cell and sensor plate size, their relationships, evaluation of ESD ring coupling, and exploration of cell and array layout approaches for achieving reduced parasitic capacitance."],"dc:identifier":["https://doi.org/10.33915/etd.1174","https://researchrepository.wvu.edu/etd/1174"],"dc:subject":["Electrical engineering","Biomedical engineering"],"dc:title":["CMOS fingerprint sensor electrostatic modeling"],"thesis:degree_discipline":["Lane Department of Computer Science and Electrical Engineering"],"thesis:degree_level":["Thesis"],"thesis:degree_name":["MS"]},"updated_at":"2026-07-24T06:15:23Z"}