Scenario-based verification and validation of dynamic UML specifications

The Unified Modeling Language (UML) is the result of the unification process of earlier object oriented models and notations. Verification and validation (V&V) tasks, as applied to UML specifications, enable early detection of analysis and design flaws prior to implementation. In this work, we address four V&V analysis methods for UML dynamic specifications, namely: Timing analysis and automatic V&V of timing constraints, automated Architectural-level Risk assessment, Performance Modeling and Fault Injection analysis. For each we present: approaches, methods and/or automated techniques. We use two case studies: a Cardiac Pacemaker and a simplified Automatic Teller Machine (ATM) banking subsystem, for illustrating the developed techniques.

Name thesis:degree_name

MS

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Lane Department of Computer Science and Electrical Engineering

Year dc:date.available

2001

Author dc:creator

• Ibrahim, Alaa El-Sayed

Contributors dc:contributor

• Hany H. Ammar.

• Electrical engineering
• Computer science

Identifier

https://researchrepository.wvu.edu/etd/1114

OAI identifier oai:identifier

oai:researchrepository.wvu.edu:etd-2117