A Reconfigurable FPGA Overlay Architecture for Matrix-Matrix Multiplication

<p>The increasing popularity of deep learning in workloads across vision, speech, and language has inspired many attempts to develop hardware accelerators for matrix-matrix multiplication. Both application-specific integrated circuits (ASICs), and field-programmable arrays (FPGAs) are used for this purpose. However, a trade-off between the two platforms is that ASICs provide little flexibility after they are manufactured while designs on FPGAs are flexible but application development on FPGAs is more time-consuming. In this work, we aim to find the balance between reconfigurability and development efficiency by designing a reconfigurable systolic architecture as an overlay on the FPGA. Our contribution to the reconfigurable systolic architectures is a multiplexer-based crossbar network that interconnects every processing element in the network. The crossbar network grants user run-time reconfigurability of the topology of the systolic array, enabling the user to specify the shape and size of the systolic architecture on-the-fly. The proposed overlay architecture achieves similar computational hardware resource usage and maximum clock frequency compared to the baseline designs.</p>

Name thesis:degree_name

Master of Science (MS)

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Computer Science & Engineering

Year dc:date.available

2022

Author dc:creator

• Chen, Zihao

• FPGA overlay
• Engineering

Statement dc:rights

• I have not registered my thesis with the U.S. Copyright Office, and do not intend to.

Language dc:language

English (en)

Identifier

https://openscholarship.wustl.edu/eng_etds/710

OAI identifier oai:identifier

oai:openscholarship.wustl.edu:eng_etds-1764