A Design for Test and Security Methodology for Integrated Circuits
type: CreativeWork
description: The costs of in-house IC fabrication have increased significantly with new technology nodes and nanoscale transistors. Many companies have outsourced their need for IC fabrication to eliminate the overhead costs associated with operating a fabrication facility. While outsourcing has its benefits, it provides opportunities for hardware Trojan (HT) injection at different design levels. Hardware Trojans and IP piracy are the new realities that must be considered for trustworthy IC design. The miniature size of HTs, coupled with their diversity and unpredictable effects, makes them difficult to detect. Even though various solutions and design methods have been proposed to address security concerns posed by HTs, a comprehensive solution is yet far from reach. Moreover, the effects of Process, Voltage, and Temperature (PVT) variations have been largely neglected in the reported solutions which may undermine their effectiveness. This dissertation presents Hardware Trojan prevention techniques that are resilient to PVT variations.In this dissertation, two new Design-For-Security (DFS) solutions for HT prevention using a layout filling technique and a layout manipulation method are presented. The first DFS technique involves occupying the unused polysilicon layer with minimum feature wires to deprive attackers of the resources needed for Trojan routing. This technique prevents attackers from inserting an active layer on the silicon substrate. Since the active layer connects to the polysilicon layer directly, if the unused poly layer is covered with minimum size wires, it becomes impossible for an attacker to rout a HT without removing a portion of the polysilicon wires. A readout circuit is used to ensure that the layer is intact and has not been tampered with. This technique can provide a complete utilization of the unused areas of the polysilicon layer. A novel tamper resilient solution is also presented as the second DFS technique to capture integrated circuits' electroma…
abstract: The costs of in-house IC fabrication have increased significantly with new technology nodes and nanoscale transistors. Many companies have outsourced their need for IC fabrication to eliminate the overhead costs associated with operating a fabrication facility. While outsourcing has its benefits, it provides opportunities for hardware Trojan (HT) injection at different design levels. Hardware Trojans and IP piracy are the new realities that must be considered for trustworthy IC design. The miniature size of HTs, coupled with their diversity and unpredictable effects, makes them difficult to detect. Even though various solutions and design methods have been proposed to address security concerns posed by HTs, a comprehensive solution is yet far from reach. Moreover, the effects of Process, Voltage, and Temperature (PVT) variations have been largely neglected in the reported solutions which may undermine their effectiveness. This dissertation presents Hardware Trojan prevention techniques that are resilient to PVT variations.In this dissertation, two new Design-For-Security (DFS) solutions for HT prevention using a layout filling technique and a layout manipulation method are presented. The first DFS technique involves occupying the unused polysilicon layer with minimum feature wires to deprive attackers of the resources needed for Trojan routing. This technique prevents attackers from inserting an active layer on the silicon substrate. Since the active layer connects to the polysilicon layer directly, if the unused poly layer is covered with minimum size wires, it becomes impossible for an attacker to rout a HT without removing a portion of the polysilicon wires. A readout circuit is used to ensure that the layer is intact and has not been tampered with. This technique can provide a complete utilization of the unused areas of the polysilicon layer. A novel tamper resilient solution is also presented as the second DFS technique to capture integrated circuits' electroma…
author: Supon, Tareq Muhammad
language: en_CA
license: http://creativecommons.org/licenses/by-nc-nd/4.0/
date published: 2021-06-18
date modified: 2026-07-27T22:04:46Z
provider: University of Windsor
publisher: Networked Digital Library of Theses and Dissertations
type: WebPage
source organization: University of Windsor

PropertyValue
property ID: Handle
value: https://hdl.handle.net/20.500.14776/9390