{"id":{"repo_id":"windsor","oai_identifier":"oai:uwindsor.scholaris.ca:20.500.14776/7141"},"canonical_url":"https://search.dev.ndltd.org/etd/windsor/oai:uwindsor.scholaris.ca:20.500.14776/7141","repository":{"repo_id":"windsor","name":"University of Windsor","base_url":"https://uwindsor.scholaris.ca/server/oai/request"},"display":{"title":"An Exploration of the Feasibility of FPGA Implementation of Face Recognition Using Eigenfaces","abstract":"Biometric identification has been a major force since 1990's. There are different types of approaches for it; one of the most significant approaches is face recognition. Over the past two decades, face recognition techniques have improved significantly, the main focus being the development of efficient algorithm. The state of art algorithms with good recognition rate are implemented using programming languages such as C++, JAVA and MATLAB, these requires a fast and computationally efficient hardware such as workstations. If the face recognition algorithms could be written in a Hardware Description Language, they could be implemented in an FPGA. In this thesis we have choose the eigenfaces algorithm, since it is simple and very efficient, this algorithm is first solved analytically, and then the architecture is designed for FPGA implementation. We then develop the Verilog module for each of these modules and test their functionality using a Verilog Simulator and finally we discuss the feasibility of FPGA implementation. Implementing the face recognition technology in an FPGA would mean that they would require relatively low power and the size is drastically reduced when compared to the workstations. They would also be much faster and efficient, since they are specifically designed for face recognition.","abstract_html":"Biometric identification has been a major force since 1990's. There are different types of approaches for it; one of the most significant approaches is face recognition. Over the past two decades, face recognition techniques have improved significantly, the main focus being the development of efficient algorithm. The state of art algorithms with good recognition rate are implemented using programming languages such as C++, JAVA and MATLAB, these requires a fast and computationally efficient hardware such as workstations. If the face recognition algorithms could be written in a Hardware Description Language, they could be implemented in an FPGA. In this thesis we have choose the eigenfaces algorithm, since it is simple and very efficient, this algorithm is first solved analytically, and then the architecture is designed for FPGA implementation. We then develop the Verilog module for each of these modules and test their functionality using a Verilog Simulator and finally we discuss the feasibility of FPGA implementation. Implementing the face recognition technology in an FPGA would mean that they would require relatively low power and the size is drastically reduced when compared to the workstations. They would also be much faster and efficient, since they are specifically designed for face recognition.","abstract_has_math":false,"creators":["Anbalagan, Vinod"],"institution":"University of Windsor","degree_name":"M.A.Sc.","degree_level":"Masters","degree_discipline":"Electrical and Computer Engineering","degree_department":null,"school":null,"contributors":["seren@uwindsor.ca"],"advisors":["Wu, Jonathan","Khalid, Mohammad A. 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There are different types of approaches for it; one of the most significant approaches is face recognition. Over the past two decades, face recognition techniques have improved significantly, the main focus being the development of efficient algorithm. The state of art algorithms with good recognition rate are implemented using programming languages such as C++, JAVA and MATLAB, these requires a fast and computationally efficient hardware such as workstations. If the face recognition algorithms could be written in a Hardware Description Language, they could be implemented in an FPGA. In this thesis we have choose the eigenfaces algorithm, since it is simple and very efficient, this algorithm is first solved analytically, and then the architecture is designed for FPGA implementation. We then develop the Verilog module for each of these modules and test their functionality using a Verilog Simulator and finally we discuss the feasibility of FPGA implementation. Implementing the face recognition technology in an FPGA would mean that they would require relatively low power and the size is drastically reduced when compared to the workstations. They would also be much faster and efficient, since they are specifically designed for face recognition."]},{"key":"dc:title","label":"Title","values":["An Exploration of the Feasibility of FPGA Implementation of Face Recognition Using Eigenfaces"]}]}],"canonical_facts":{"dc:contributor":["seren@uwindsor.ca"],"dc:contributor.advisor":["Wu, Jonathan","Khalid, Mohammad A. S."],"dc:creator":["Anbalagan, Vinod"],"dc:date.accessioned":["2025-07-03 13:59"],"dc:date.available":["2019-12-18 13:52","2025-07-03T17:59:33Z"],"dc:date.issued":["2012-01-01"],"dc:description.abstract":["Biometric identification has been a major force since 1990's. There are different types of approaches for it; one of the most significant approaches is face recognition. Over the past two decades, face recognition techniques have improved significantly, the main focus being the development of efficient algorithm. The state of art algorithms with good recognition rate are implemented using programming languages such as C++, JAVA and MATLAB, these requires a fast and computationally efficient hardware such as workstations. If the face recognition algorithms could be written in a Hardware Description Language, they could be implemented in an FPGA. In this thesis we have choose the eigenfaces algorithm, since it is simple and very efficient, this algorithm is first solved analytically, and then the architecture is designed for FPGA implementation. We then develop the Verilog module for each of these modules and test their functionality using a Verilog Simulator and finally we discuss the feasibility of FPGA implementation. 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