{"id":{"repo_id":"windsor","oai_identifier":"oai:uwindsor.scholaris.ca:20.500.14776/602"},"canonical_url":"https://search.dev.ndltd.org/etd/windsor/oai:uwindsor.scholaris.ca:20.500.14776/602","repository":{"repo_id":"windsor","name":"University of Windsor","base_url":"https://uwindsor.scholaris.ca/server/oai/request"},"display":{"title":"An hybrid architecture for multi-layer feed-forward neural networks.","abstract":"Multi-layer feed-forward neural networks have the capability to classify and generalize, which are not achievable with other methods. The complete exploitation of their potential to full limit requires efficient hardware implementation. The two main problems of hardware realization; easy long term storage of synaptic weights and massive interconnections, are addressed and solved by the mixed signal architecture for implementation of feed-forward neural network. The hybrid architecture is analyzed and implemented in 0.5 micron CMOS technology. The analog processing blocks have been designed in current mode analog CMOS and the synaptic weights and threshold values are stored in digital ROM.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis1999 .A36. Source: Masters Abstracts International, Volume: 39-02, page: 0557. Adviser: M. Ahmadi. Thesis (M.A.Sc.)--University of Windsor (Canada), 1999.","abstract_html":"Multi-layer feed-forward neural networks have the capability to classify and generalize, which are not achievable with other methods. The complete exploitation of their potential to full limit requires efficient hardware implementation. The two main problems of hardware realization; easy long term storage of synaptic weights and massive interconnections, are addressed and solved by the mixed signal architecture for implementation of feed-forward neural network. The hybrid architecture is analyzed and implemented in 0.5 micron CMOS technology. The analog processing blocks have been designed in current mode analog CMOS and the synaptic weights and threshold values are stored in digital ROM.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis1999 .A36. Source: Masters Abstracts International, Volume: 39-02, page: 0557. Adviser: M. Ahmadi. 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