{"id":{"repo_id":"windsor","oai_identifier":"oai:uwindsor.scholaris.ca:20.500.14776/1038"},"canonical_url":"https://search.dev.ndltd.org/etd/windsor/oai:uwindsor.scholaris.ca:20.500.14776/1038","repository":{"repo_id":"windsor","name":"University of Windsor","base_url":"https://uwindsor.scholaris.ca/server/oai/request"},"display":{"title":"FPGA Implementation of Blob Recognition","abstract":"Real-time embedded vision systems can be used in a wide range of applications and therefore the demand has been increasing for them. In this thesis, an FPGA-based embedded vision system capable of recognizing objects in real time is presented. The proposed system architecture consists of multiple Intellectual Properties (IPs), which are used as a set of complex instructions by an integrated 32-bit CPU Microblaze. Each IP is tailored specifically to meet the needs of the application and at the same time to consume the minimum FPGA logic resources. Integrating both hardware and software on a single FPGA chip, this system can achieve the real-time performance of full VGA video processing at 32 frames per second (fps). In addition, this work comes up with a new method called Dual Connected Component Labelling (DCCL) suitable for FPGA implementation.","abstract_html":"Real-time embedded vision systems can be used in a wide range of applications and therefore the demand has been increasing for them. In this thesis, an FPGA-based embedded vision system capable of recognizing objects in real time is presented. The proposed system architecture consists of multiple Intellectual Properties (IPs), which are used as a set of complex instructions by an integrated 32-bit CPU Microblaze. Each IP is tailored specifically to meet the needs of the application and at the same time to consume the minimum FPGA logic resources. Integrating both hardware and software on a single FPGA chip, this system can achieve the real-time performance of full VGA video processing at 32 frames per second (fps). In addition, this work comes up with a new method called Dual Connected Component Labelling (DCCL) suitable for FPGA implementation.","abstract_has_math":false,"creators":["Xiong, Jian"],"institution":"University of Windsor","degree_name":"M.A.Sc.","degree_level":"Masters","degree_discipline":"Electrical and Computer Engineering","degree_department":null,"school":null,"contributors":[],"advisors":["Q. M. Jonathan, Wu (Electrical and Computer Engineering)"],"committee_chairs":[],"committee_members":[],"year":2011,"date_issued":"2011-01-01","date_published":"2011-01-01","updated_at":"2026-07-27T22:04:36Z","subjects":[],"languages":["en_CA"],"rights":[],"rights_urls":["http://creativecommons.org/licenses/by-nc-nd/4.0/"],"identifier_entries":[]},"links":{"outbound_url":"https://hdl.handle.net/20.500.14776/1038","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.advisor","label":"Advisor","values":["Q. M. Jonathan, Wu (Electrical and Computer Engineering)"]},{"key":"dc:creator","label":"Author","values":["Xiong, Jian"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2025-06-12 11:13"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2012-10-26 7:17","2025-06-12T15:13:38Z"]},{"key":"dc:date.issued","label":"Date","values":["2011-01-01"]},{"key":"dc:type","label":"Dc Type","values":["text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical and Computer Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Masters"]},{"key":"thesis:degree_name","label":"Degree Name","values":["M.A.Sc."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Windsor"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language.iso","label":"Language (ISO)","values":["en_CA"]},{"key":"dc:rights","label":"Dc Rights","values":["http://creativecommons.org/licenses/by-nc-nd/4.0/"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.uri","label":"Identifier URI","values":["https://hdl.handle.net/20.500.14776/1038"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["Real-time embedded vision systems can be used in a wide range of applications and therefore the demand has been increasing for them. In this thesis, an FPGA-based embedded vision system capable of recognizing objects in real time is presented. The proposed system architecture consists of multiple Intellectual Properties (IPs), which are used as a set of complex instructions by an integrated 32-bit CPU Microblaze. Each IP is tailored specifically to meet the needs of the application and at the same time to consume the minimum FPGA logic resources. Integrating both hardware and software on a single FPGA chip, this system can achieve the real-time performance of full VGA video processing at 32 frames per second (fps). In addition, this work comes up with a new method called Dual Connected Component Labelling (DCCL) suitable for FPGA implementation."]},{"key":"dc:title","label":"Title","values":["FPGA Implementation of Blob Recognition"]}]}],"canonical_facts":{"dc:contributor.advisor":["Q. M. Jonathan, Wu (Electrical and Computer Engineering)"],"dc:creator":["Xiong, Jian"],"dc:date.accessioned":["2025-06-12 11:13"],"dc:date.available":["2012-10-26 7:17","2025-06-12T15:13:38Z"],"dc:date.issued":["2011-01-01"],"dc:description.abstract":["Real-time embedded vision systems can be used in a wide range of applications and therefore the demand has been increasing for them. In this thesis, an FPGA-based embedded vision system capable of recognizing objects in real time is presented. The proposed system architecture consists of multiple Intellectual Properties (IPs), which are used as a set of complex instructions by an integrated 32-bit CPU Microblaze. Each IP is tailored specifically to meet the needs of the application and at the same time to consume the minimum FPGA logic resources. Integrating both hardware and software on a single FPGA chip, this system can achieve the real-time performance of full VGA video processing at 32 frames per second (fps). In addition, this work comes up with a new method called Dual Connected Component Labelling (DCCL) suitable for FPGA implementation."],"dc:identifier.uri":["https://hdl.handle.net/20.500.14776/1038"],"dc:language.iso":["en_CA"],"dc:rights":["http://creativecommons.org/licenses/by-nc-nd/4.0/"],"dc:title":["FPGA Implementation of Blob Recognition"],"dc:type":["text"],"thesis:degree_discipline":["Electrical and Computer Engineering"],"thesis:degree_level":["Masters"],"thesis:degree_name":["M.A.Sc."],"thesis:institution_name":["University of Windsor"]},"updated_at":"2026-07-27T22:04:36Z"}