{"id":{"repo_id":"washington","oai_identifier":"oai:digital.lib.washington.edu:1773/33811"},"canonical_url":"https://search.dev.ndltd.org/etd/washington/oai:digital.lib.washington.edu:1773/33811","repository":{"repo_id":"washington","name":"University of Washington","base_url":"https://digital.lib.washington.edu/server/oai/request"},"display":{"title":"High-Voltage Compliant, Electrode-Invariant Neural Stimulation Electronics Compatible with Low-Voltage, Bulk-CMOS Integration","abstract":"This work explores the challenges of implementing practical, electrical neural stimulation interfaces using modern silicon CMOS technologies. To overcome said challenges, which stem from the discrepancy between the low-voltage limitations of modern CMOS devices and the large stimulation voltages often observed at response-evoking stimulus levels, a new stimulator front-end is proposed. The high-voltage compliant front-end can reliably drive biphasic, constant-current stimulus through a wide range of electrode impedances while being safely implemented in a low-voltage, bulk-CMOS technology. The topology of the front-end is based on a sink-regulated H-bridge. Stimulus current is supplied using specialized, fully-integrated dynamic voltage supplies (DVSs), which are controlled in closed-loop to have an output voltage approximately equal to the voltage of the electrode each supplies stimulus to. The entire stimulus waveform is regulated by a single, low-voltage current-DAC, which can safely interface with the electrodes (which may be at high voltages) via specialized high-voltage adapter (HVA) circuits. To account for “capacitive-looking” electrodes and to provide unique, “electrode-invariant” performance, the front-end uses the balancing stimulus current to discharge the electrode-tissue-interface impedance (ZE), and only after full ZE discharge has been detected is a DVS used to supply the remaining balancing stimulus. In this thesis the described front-end topology and the enabling high-voltage operating circuits are presented and discussed in detail. Additionally, a stand-alone DVS circuit has been fabricated in 65nm bulk-CMOS, demonstrating the power-supplying and transient performance required by the proposed stimulator design. Another chip, featuring the entire integrated neural stimulator front-end, has also been designed in 65nm bulk-CMOS, with post-layout simulations showing ±11V compliance (approximately) across a 50μA to 2mA stimulus amplitude range. The efficacy of the proposed integrated electronics in potential neural stimulation applications is also explored using a board-level prototype and in-vivo evaluation.","abstract_html":"This work explores the challenges of implementing practical, electrical neural stimulation interfaces using modern silicon CMOS technologies. To overcome said challenges, which stem from the discrepancy between the low-voltage limitations of modern CMOS devices and the large stimulation voltages often observed at response-evoking stimulus levels, a new stimulator front-end is proposed. The high-voltage compliant front-end can reliably drive biphasic, constant-current stimulus through a wide range of electrode impedances while being safely implemented in a low-voltage, bulk-CMOS technology. The topology of the front-end is based on a sink-regulated H-bridge. Stimulus current is supplied using specialized, fully-integrated dynamic voltage supplies (DVSs), which are controlled in closed-loop to have an output voltage approximately equal to the voltage of the electrode each supplies stimulus to. The entire stimulus waveform is regulated by a single, low-voltage current-DAC, which can safely interface with the electrodes (which may be at high voltages) via specialized high-voltage adapter (HVA) circuits. To account for “capacitive-looking” electrodes and to provide unique, “electrode-invariant” performance, the front-end uses the balancing stimulus current to discharge the electrode-tissue-interface impedance (ZE), and only after full ZE discharge has been detected is a DVS used to supply the remaining balancing stimulus. In this thesis the described front-end topology and the enabling high-voltage operating circuits are presented and discussed in detail. Additionally, a stand-alone DVS circuit has been fabricated in 65nm bulk-CMOS, demonstrating the power-supplying and transient performance required by the proposed stimulator design. Another chip, featuring the entire integrated neural stimulator front-end, has also been designed in 65nm bulk-CMOS, with post-layout simulations showing ±11V compliance (approximately) across a 50μA to 2mA stimulus amplitude range. The efficacy of the proposed integrated electronics in potential neural stimulation applications is also explored using a board-level prototype and in-vivo evaluation.","abstract_has_math":false,"creators":["Pepin, Eric Philip"],"institution":null,"degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":null,"school":null,"contributors":[],"advisors":["Rudell, Jacques C"],"committee_chairs":[],"committee_members":[],"year":2015,"date_issued":"2015-09-29","date_published":"2015-09-29","updated_at":"2026-07-24T05:58:07Z","subjects":["high-voltage; low-voltage CMOS; neural stimulation"],"languages":["en_US"],"rights":["Copyright is held by the individual authors."],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/1773/33811","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.advisor","label":"Advisor","values":["Rudell, Jacques C"]},{"key":"dc:creator","label":"Author","values":["Pepin, Eric Philip"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2015-09-29T18:02:25Z"]},{"key":"dc:date.issued","label":"Date","values":["2015-09-29"]},{"key":"dc:type","label":"Dc Type","values":["Thesis"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["high-voltage; low-voltage CMOS; neural stimulation"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language.iso","label":"Language (ISO)","values":["en_US"]},{"key":"dc:rights","label":"Dc Rights","values":["Copyright is held by the individual authors."]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.other","label":"Dc Identifier Other","values":["Pepin_washington_0250O_15045.pdf"]},{"key":"dc:identifier.uri","label":"Identifier URI","values":["http://hdl.handle.net/1773/33811"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Thesis (Master's)--University of Washington, 2015"]},{"key":"dc:description.abstract","label":"Abstract","values":["This work explores the challenges of implementing practical, electrical neural stimulation interfaces using modern silicon CMOS technologies. To overcome said challenges, which stem from the discrepancy between the low-voltage limitations of modern CMOS devices and the large stimulation voltages often observed at response-evoking stimulus levels, a new stimulator front-end is proposed. The high-voltage compliant front-end can reliably drive biphasic, constant-current stimulus through a wide range of electrode impedances while being safely implemented in a low-voltage, bulk-CMOS technology. The topology of the front-end is based on a sink-regulated H-bridge. Stimulus current is supplied using specialized, fully-integrated dynamic voltage supplies (DVSs), which are controlled in closed-loop to have an output voltage approximately equal to the voltage of the electrode each supplies stimulus to. The entire stimulus waveform is regulated by a single, low-voltage current-DAC, which can safely interface with the electrodes (which may be at high voltages) via specialized high-voltage adapter (HVA) circuits. To account for “capacitive-looking” electrodes and to provide unique, “electrode-invariant” performance, the front-end uses the balancing stimulus current to discharge the electrode-tissue-interface impedance (ZE), and only after full ZE discharge has been detected is a DVS used to supply the remaining balancing stimulus. In this thesis the described front-end topology and the enabling high-voltage operating circuits are presented and discussed in detail. Additionally, a stand-alone DVS circuit has been fabricated in 65nm bulk-CMOS, demonstrating the power-supplying and transient performance required by the proposed stimulator design. Another chip, featuring the entire integrated neural stimulator front-end, has also been designed in 65nm bulk-CMOS, with post-layout simulations showing ±11V compliance (approximately) across a 50μA to 2mA stimulus amplitude range. The efficacy of the proposed integrated electronics in potential neural stimulation applications is also explored using a board-level prototype and in-vivo evaluation."]},{"key":"dc:format.mimetype","label":"Dc Format Mimetype","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["High-Voltage Compliant, Electrode-Invariant Neural Stimulation Electronics Compatible with Low-Voltage, Bulk-CMOS Integration"]}]}],"canonical_facts":{"dc:contributor.advisor":["Rudell, Jacques C"],"dc:creator":["Pepin, Eric Philip"],"dc:date.accessioned":["2015-09-29T18:02:25Z"],"dc:date.issued":["2015-09-29"],"dc:description":["Thesis (Master's)--University of Washington, 2015"],"dc:description.abstract":["This work explores the challenges of implementing practical, electrical neural stimulation interfaces using modern silicon CMOS technologies. To overcome said challenges, which stem from the discrepancy between the low-voltage limitations of modern CMOS devices and the large stimulation voltages often observed at response-evoking stimulus levels, a new stimulator front-end is proposed. The high-voltage compliant front-end can reliably drive biphasic, constant-current stimulus through a wide range of electrode impedances while being safely implemented in a low-voltage, bulk-CMOS technology. The topology of the front-end is based on a sink-regulated H-bridge. Stimulus current is supplied using specialized, fully-integrated dynamic voltage supplies (DVSs), which are controlled in closed-loop to have an output voltage approximately equal to the voltage of the electrode each supplies stimulus to. The entire stimulus waveform is regulated by a single, low-voltage current-DAC, which can safely interface with the electrodes (which may be at high voltages) via specialized high-voltage adapter (HVA) circuits. To account for “capacitive-looking” electrodes and to provide unique, “electrode-invariant” performance, the front-end uses the balancing stimulus current to discharge the electrode-tissue-interface impedance (ZE), and only after full ZE discharge has been detected is a DVS used to supply the remaining balancing stimulus. In this thesis the described front-end topology and the enabling high-voltage operating circuits are presented and discussed in detail. Additionally, a stand-alone DVS circuit has been fabricated in 65nm bulk-CMOS, demonstrating the power-supplying and transient performance required by the proposed stimulator design. Another chip, featuring the entire integrated neural stimulator front-end, has also been designed in 65nm bulk-CMOS, with post-layout simulations showing ±11V compliance (approximately) across a 50μA to 2mA stimulus amplitude range. The efficacy of the proposed integrated electronics in potential neural stimulation applications is also explored using a board-level prototype and in-vivo evaluation."],"dc:format.mimetype":["application/pdf"],"dc:identifier.other":["Pepin_washington_0250O_15045.pdf"],"dc:identifier.uri":["http://hdl.handle.net/1773/33811"],"dc:language.iso":["en_US"],"dc:rights":["Copyright is held by the individual authors."],"dc:subject":["high-voltage; low-voltage CMOS; neural stimulation"],"dc:title":["High-Voltage Compliant, Electrode-Invariant Neural Stimulation Electronics Compatible with Low-Voltage, Bulk-CMOS Integration"],"dc:type":["Thesis"]},"updated_at":"2026-07-24T05:58:07Z"}