Power Management Schemes for Ultra Low Power Biomedical Devices

Device power dissipation has grown exponentially due to the rapid transistor technology scaling and increased circuit complexity. Motivated by the ultra low power requirements of emerging implantable and wearable biomedical devices, novel power management schemes are presented in this thesis to increase device run-time. The schemes involve several techniques suitable for ultra low power biomedical integrated circuit design. This thesis presents a combination of two novel power reduction schemes to reduce the total device power comprising of dynamic and static power dissipation. One of the schemes used is the supply voltage (Vdd) scaling, also known as Dynamic Voltage Scaling (DVS). DVS is an effective scheme to reduce dynamic power (Pdynamic) dissipation. The DVS architecture primarily consists of a DC-DC power regulator which is customised to handle scaling variability of the Vdd. The implemented DVS can dynamically vary the Vdd from 300 mV to 1.2 V. The second scheme presented in this thesis to reduce static power (Pstatic) dissipation is threshold voltage scaling. The variable threshold keeper technique is used to perform threshold voltage scaling, which comprises of a keeper transistor whose threshold voltage is scaled by a body bias generator. The use of the keeper transistor increases the device noise immunity. This combination of supply and threshold voltage scaling techniques offers a further reduction in the overall device power dissipation and enhances reliability without degrading circuit speed. A power reduction of 23% to 31% is achievable with up to 90% efficiency. The thesis discusses the primary design challenges of ultra low power biomedical devices. System and circuit levels design techniques are described which help meeting the stringent requirements imposed by the biomedical environment. This thesis presents a new DVS architecture and investigates the effect of lowering the supply voltage combined with threshold voltage scaling on dynamic power dissipation using 0.13 μm ST-Microelectronic® 6-metal layer CMOS dual- process technology.

Name dc:type.qualificationname

phd

Level dc:type.qualificationlevel

doctoral

Grantor dc:publisher.institution

Victoria University

Year dc:date.issued

2007

Author dc:creator

• Fitrio, David

• 290000 Engineering and Technology
• School of Engineering and Science

Language dc:language

en