Towards Using Free Memory to Improve Microarchitecture Performance

A computer system's memory is designed to accommodate the worst-case workloads with the highest memory requirement; as such, memory is underutilized when a system runs workloads with common-case memory requirements. Through a large-scale study of four production HPC systems, we find that memory underutilization problem in HPC systems is very severe. As unused memory is wasted memory, we propose exposing a compute node's unused memory to its CPU(s) through a user-transparent CPU-OS codesign. This can enable many new microarchitecture techniques that transparently leverage unused memory locations to help improve microarchitecture performance. We refer to these techniques as Free-memory-aware Microarchitecture Techniques (FMTs). In the context of HPC systems, we present a detailed example of an FMT called Free-memory-aware Replication (FMR). FMR replicates in-use data to unused memory locations to effectively reduce average memory read latency. On average across five HPC benchmark suites, FMR provides 13% performance and 8% system-level energy improvement.

Name thesis:degree_name

M.S.

Level thesis:degree_level

masters

Discipline thesis:degree_discipline

Computer Engineering

Department dc:contributor.department

Electrical and Computer Engineering

Grantor dc:publisher

Virginia Tech

Year dc:date.issued

2020

Author dc:creator

• Panwar, Gagandeep

Chairs dc:contributor.committeechair

• Ravindran, Binoy
• Jian, Xun

Committee member dc:contributor.committeemember

• Patterson, Cameron D.

• Computer Architecture
• Memory
• DRAM
• HPC systems

Statement dc:rights

• Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International

Licence dc:rights.uri

• http://creativecommons.org/licenses/by-nc-nd/4.0/

Language dc:language.iso

en

Handle dc:identifier.uri

http://hdl.handle.net/10919/98745

OAI identifier oai:identifier

oai:vtechworks.lib.vt.edu:10919/98745