Back to results

Virginia Polytechnic Institute and State University

Multi-processor logic simulation at the chip level

Abstract

dc:description.abstract

This dissertation presents the design and development of a multi-processor logic simulator. After an introduction to parallel processing, the concept of distributed simulation is described as well as the possibility of deadlock in a distributed system. It is proven that the proposed system does not deadlock. Next, the modeling techniques are discussed along with the timing mechanisms used for logic simulation. A new approach, namely process oriented simulation is studied in depth. It is shown that modeling for this kind of simulation is more efficient regarding modeling ease, computer memory and simulation time, than existing simulation methods. The hardware design of the multi-processor system and the algorithms for synchronization and signal interchange between the processors are presented next. An algorithm for an efficient partitioning of the digital network to be simulated among the processors of the system is also described. Apart from the simulation of a single digital network, the simulator can also be used for fault simulation and design verification. Regarding fault simulation, the fault injection and fault detection techniques are presented. The experimental results obtained by running the multi-processor simulator are compared with the theoretical estimates as well as with results obtained by other multi-processor systems. The comparison shows that the proposed simulator exhibits the estimated performance. Finally, the design of a common bus interface is given. This interface will connect the processors of the system directly without the intervention of a hard disk which was used for the development and testing of the system.

Degree

thesis:*
Name thesis:degree_name
Ph. D.
Level thesis:degree_level
doctoral
Discipline thesis:degree_discipline
Electrical Engineering
Department dc:contributor.department
Electrical Engineering
Grantor dc:publisher
Virginia Polytechnic Institute and State University
Year dc:date.issued
1986

Author and committee

dc:creator, dc:contributor.*
Author dc:creator
  • Roumeliotis, Emmanuel
Chair dc:contributor.committeechair
  • Armstrong, James R.
Committee members dc:contributor.committeemember
  • Besieris, Ioannis M.
  • Brown, E.
  • Gray, G.
  • Nunnally, Charles E.

Rights

dc:rights
Statement dc:rights
  • In Copyright
Language dc:language.iso
en_US

Identifiers

dc:identifier.*
Handle dc:identifier.uri
http://hdl.handle.net/10919/71180
OAI identifier oai:identifier
oai:vtechworks.lib.vt.edu:10919/71180

Chain of custody

source
Harvested from
Virginia Tech
Base URL
vtechworks.lib.vt.edu/oai/request
Last updated
2026-07-22
Source record
OAI-PMH GetRecord
related terms
citation

Roumeliotis, Emmanuel. Multi-processor logic simulation at the chip level. doctoral thesis, Virginia Polytechnic Institute and State University, 1986. http://hdl.handle.net/10919/71180