{"id":{"repo_id":"vt","oai_identifier":"oai:vtechworks.lib.vt.edu:10919/46135"},"canonical_url":"https://search.dev.ndltd.org/etd/vt/oai:vtechworks.lib.vt.edu:10919/46135","repository":{"repo_id":"vt","name":"Virginia Tech","base_url":"https://vtechworks.lib.vt.edu/oai/request"},"display":{"title":"Computation of parasitics in multilayer hybrid microelectronics","abstract":"Layout parasitics result from electromagnetic interaction between circuit metalizations used to connect devices on the hybrid circuit. Three linked programs have been written to calculate the capacitance and inductance between circuit metalizations. (1) XT Editor A user friendly hybrid circuit layout editor which enables the user to create circuit layouts and select portions of the circuit for parasitic computation. (2) XT Mesh A two and three dimensional fully automatic mesh generator. The mesh generator combines the quadrant/octant subdivision method and Watson's algorithm in a four step process. Initial triangulations are created and cell compatibility is ensured using an alternating initial mesh scheme. This method produces substantial time savings by avoiding the use of data tree structures and stringent cell size rules. (3) XT Field Solver A two and three dimensional finite element quasi-TEM solver which calculates the capacitance and inductance between circuit metalizations.","abstract_html":"Layout parasitics result from electromagnetic interaction between circuit metalizations used to connect devices on the hybrid circuit. Three linked programs have been written to calculate the capacitance and inductance between circuit metalizations. (1) XT Editor A user friendly hybrid circuit layout editor which enables the user to create circuit layouts and select portions of the circuit for parasitic computation. (2) XT Mesh A two and three dimensional fully automatic mesh generator. The mesh generator combines the quadrant/octant subdivision method and Watson's algorithm in a four step process. Initial triangulations are created and cell compatibility is ensured using an alternating initial mesh scheme. This method produces substantial time savings by avoiding the use of data tree structures and stringent cell size rules. (3) XT Field Solver A two and three dimensional finite element quasi-TEM solver which calculates the capacitance and inductance between circuit metalizations.","abstract_has_math":false,"creators":["Marchand, Roger T."],"institution":"Virginia Tech","degree_name":"Master of Science","degree_level":"masters","degree_discipline":"Electrical Engineering","degree_department":"Electrical Engineering","school":null,"contributors":[],"advisors":[],"committee_chairs":[],"committee_members":[],"year":1992,"date_issued":"1992","date_published":"1992","updated_at":"2026-07-22T22:19:35Z","subjects":[],"languages":["en"],"rights":["In Copyright"],"rights_urls":["http://rightsstatements.org/vocab/InC/1.0/"],"identifier_entries":[{"key":"dc:identifier.other","label":"Dc Identifier Other","values":["etd-12052009-020108"],"render_values":[{"text":"etd-12052009-020108","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/10919/46135","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.department","label":"Department","values":["Electrical Engineering"]},{"key":"dc:creator","label":"Author","values":["Marchand, Roger T."]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2014-03-14T21:51:03Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2014-03-14T21:51:03Z","2009-12-05"]},{"key":"dc:date.issued","label":"Date","values":["1992"]},{"key":"dc:publisher","label":"Institution","values":["Virginia Tech"]},{"key":"dc:type","label":"Dc Type","values":["Thesis"]},{"key":"dc:type.dcmitype","label":"Dc Type Dcmitype","values":["Text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["masters"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Master of Science"]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["Virginia Polytechnic Institute and State University"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language.iso","label":"Language (ISO)","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["In Copyright"]},{"key":"dc:rights.uri","label":"Rights URI","values":["http://rightsstatements.org/vocab/InC/1.0/"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.other","label":"Dc Identifier Other","values":["etd-12052009-020108"]},{"key":"dc:identifier.uri","label":"Identifier URI","values":["http://hdl.handle.net/10919/46135"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["Layout parasitics result from electromagnetic interaction between circuit metalizations used to connect devices on the hybrid circuit. Three linked programs have been written to calculate the capacitance and inductance between circuit metalizations. (1) XT Editor A user friendly hybrid circuit layout editor which enables the user to create circuit layouts and select portions of the circuit for parasitic computation. (2) XT Mesh A two and three dimensional fully automatic mesh generator. The mesh generator combines the quadrant/octant subdivision method and Watson's algorithm in a four step process. Initial triangulations are created and cell compatibility is ensured using an alternating initial mesh scheme. This method produces substantial time savings by avoiding the use of data tree structures and stringent cell size rules. (3) XT Field Solver A two and three dimensional finite element quasi-TEM solver which calculates the capacitance and inductance between circuit metalizations."]},{"key":"dc:description.degree","label":"Dc Description Degree","values":["Master of Science"]},{"key":"dc:format.medium","label":"Dc Format Medium","values":["BTD"]},{"key":"dc:format.mimetype","label":"Dc Format Mimetype","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Computation of parasitics in multilayer hybrid microelectronics"]}]}],"canonical_facts":{"dc:contributor.department":["Electrical Engineering"],"dc:creator":["Marchand, Roger T."],"dc:date.accessioned":["2014-03-14T21:51:03Z"],"dc:date.available":["2014-03-14T21:51:03Z","2009-12-05"],"dc:date.issued":["1992"],"dc:description.abstract":["Layout parasitics result from electromagnetic interaction between circuit metalizations used to connect devices on the hybrid circuit. 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